H01L21/02307

Interconnect structure for semiconductor device and methods of fabrication thereof

Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

PROCESS FOR FABRICATING SILICON NANOSTRUCTURES
20200273950 · 2020-08-27 ·

A process for etching a substrate comprising polycrystalline silicon to form silicon nanostructures includes depositing metal on top of the substrate and contacting the metallized substrate with an etchant aqueous solution comprising about 2 to about 49 weight percent HF and an oxidizing agent.

Apparatus and method for treating substrate

Disclosed are an apparatus and a method for treating a substrate. The method includes repeatedly rotating the substrate alternately at a first speed and at a second speed while the treatment liquid is supplied, and the second speed is higher than the first speed.

Surface modification layer for conductive feature formation

Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

Process for fabricating silicon nanostructures

A process for etching a substrate comprising polycrystalline silicon to form silicon nanostructures includes depositing metal on top of the substrate and contacting the metallized substrate with an etchant aqueous solution comprising about 2 to about 49 weight percent HF and an oxidizing agent.

Solution deposition method for forming metal oxide or metal hydroxide layer

A solution deposition method includes: applying a liquid precursor solution to a substrate, the precursor solution including an oxide of a first metal, a hydroxide of the first metal, or a combination thereof, dissolved in an aqueous ammonia solution; evaporating the precursor solution to directly form a solid seed layer on the substrate, the seed layer including an oxide of the first metal, a hydroxide of the first metal, or a combination thereof, the seed layer being substantially free of organic compounds; and growing a bulk layer on the substrate, using the seed layer as a growth site or a nucleation site.

INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHODS OF FABRICATION THEREOF

Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

Methods of Forming Metal Gates

A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

Substrate processing method and substrate processing apparatus

A substrate processing method includes a liquid film forming step of forming a liquid film of an organic solvent with which a whole area of an upper surface of a substrate is covered in order to replace a processing liquid existing on the upper surface with an organic solvent liquid, a thin film holding step of thinning the liquid film of the organic solvent by rotating the substrate at a first high rotational speed while keeping surroundings of the whole area of the upper surface in an atmosphere of an organic solvent vapor and holding a resulting thin film of the organic solvent on the upper surface, and a thin-film removing step of removing the thin film from the upper surface after the thin film holding step, and the thin-film removing step includes a high-speed rotation step of rotating the substrate at a second high rotational speed.

Surface Modification Layer for Conductive Feature Formation
20200105587 · 2020-04-02 ·

Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.