An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control-gate regions. Charge-storage material of individual memory cells extend elevationally along individual of the control-gate regions of the wordline levels and do not extend elevationally along the insulative levels. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions of the wordline levels laterally through which charge migration between the individual control-gate regions and the charge-storage material is blocked. Channel material extends elevationally along the stack and is laterally spaced from the charge-storage material by insulative charge-passage material. All of the charge-storage material of individual of the elevationally-extending strings of memory cells is laterally outward of all of the insulative charge-passage material of the individual elevationally-extending strings of memory cells. Other embodiments, including method embodiments, are disclosed.

A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

A method for manufacturing a bonded SOI wafer by bonding a bond wafer and a base wafer, each composed of a silicon single crystal, via an insulator film, including the steps of: depositing a polycrystalline silicon layer on the bonding surface side of the base wafer, polishing a surface of the polycrystalline silicon layer, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the polycrystalline silicon layer of the base wafer and the bond wafer via the insulator film, and thinning the bonded bond wafer to form an SOI layer; As a result, it is possible to provide a method for manufacturing a bonded SOI wafer which can prevent single-crystallization of polycrystalline silicon while suppressing an increase of the warpage of a base wafer even when the polycrystalline silicon layer to function as a carrier trap layer is deposited sufficiently thick.

A method of forming an oxide layer includes the following steps. A substrate is provided. A surface of the substrate is treated to form an oxygen ion-rich surface. A spin-on-dielectric layer is formed on the oxygen ion-rich surface of the substrate. The present invention also provides a method of forming an oxide layer including the following steps. A substrate is provided. A surface of the substrate is treated with a hydrogen peroxide (H.sub.2O.sub.2) solution or a surface of the substrate is treated with oxygen containing gas, to form an oxygen ion-rich surface. A spin-on-dielectric layer is formed on the oxygen ion-rich surface of the substrate.

The present invention provides a method for preparing a dielectric layer on a surface of a wafer, a wafer structure, and a method for shaping a bump. The preparation method includes: providing a wafer; forming an alignment mark on the wafer, the thickness of the alignment mark being not less than 0.3 ?m; and forming a dielectric layer on the wafer where the alignment mark is formed. In the present application, before the dielectric layer is shaped on a surface of the wafer, the alignment mark is prepared in advance on the surface of the wafer, thereby avoiding the need of reworking due to an invisible alignment mark in a preparation stage of the dielectric layer, and ensuring the continuity of the process.

Method of doping a semiconductor sample in a uniform and carbon-free way, wherein said sample has a surface, comprising the following steps: A. removing oxides from at least part of the said surface; B. dip coating said at least part of the surface of the sample in a dopant based carbon-free solution of at least one dopant based carbon free substance diluted in water, wherein said at least one dopant based carbon free substance has a molecule comprising at least one dopant atom, wherein the dip coating is achieved by heating said dopant based carbon-free solution at a dip coating temperature from 65% to 100% of the boiling temperature of said dopant based carbon-free solution, thereby a self-assembled mono-layer including dopant atoms is formed; C. annealing said sample, wherein the annealing is configured to cause said dopant atoms included in said self-assembled mono-layer to be diffused into the sample.

Provided is a material composition and method for substrate modification. A substrate is patterned to include a plurality of features. The plurality of features includes a first subset of features having one or more substantially inert surfaces. In various embodiments, a priming material is deposited over the substrate, over the plurality of features, and over the one or more substantially inert surfaces. By way of example, the deposited priming material bonds at least to the one or more substantially inert surfaces. Additionally, the deposited priming material provides a modified substrate surface. After depositing the priming material, a layer is spin-coated over the modified substrate surface, where the spin-coated layer is substantially planar.

Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

Disclosed are pre-wetting apparatus designs and methods. In some embodiments, a pre-wetting apparatus includes a degasser, a process chamber, and a controller. The process chamber includes a wafer holder configured to hold a wafer substrate, a vacuum port configured to allow formation of a subatmospheric pressure in the process chamber, and a fluid inlet coupled to the degasser and configured to deliver a degassed pre-wetting fluid onto the wafer substrate at a velocity of at least about 7 meters per second whereby particles on the wafer substrate are dislodged and at a flow rate whereby dislodged particles are removed from the wafer substrate. The controller includes program instructions for forming a wetting layer on the wafer substrate in the process chamber by contacting the wafer substrate with the degassed pre-wetting fluid admitted through the fluid inlet at a flow rate of at least about 0.4 liters per minute.

Compositions useful for the passivation of germanium-containing materials on a microelectronic device having same thereon.