A method for in-situ dry cleaning of a SiGe semiconductor surface doses the SiGe surface with ex-situ wet HF in a clean ambient environment or in-situ dosing with gaseous NH.sub.4F to remove oxygen containing contaminants. Dosing the SiGe surface with atomic H removes carbon containing contaminants. Low temperature annealing pulls the surface flat. Passivating the SiGe semiconductor surface with H.sub.2O.sub.2 vapor for a sufficient time and concentration forms an a oxygen monolayer(s) of —OH sites on the SiGe. Second annealing the SiGe semiconductor surface is conducted at a temperature below that which would induce dopant diffusion. A method for in-situ dry cleaning of a SiGe semiconductor surface, ex-situ degreases the Ge containing semiconductor surface and removes organic contaminants. The surface is then dosed with HF(aq) or NH4F(g) generated via NH.sub.3+NH or NF.sub.3 with H.sub.2 or H.sub.2O to remove oxygen containing contaminants. In-situ dosing of the SiGe surface with atomic H removes carbon containing contaminants.

A method is described for an area selective deposition (ASD) process that is a dielectric on dielectric (DoD) ASD process performed over a major surface of a semiconductor substrate. The substrate comprises a conductive material embedded in a first dielectric layer, and the major surface comprises a conductive surface and a dielectric surface of the first dielectric layer. In this method, a metal-containing capping layer is formed selectively over the dielectric surface of the first dielectric layer. In a subsequent process step, a second dielectric layer is formed from the metal-containing capping layer. Hence, the DoD ASD process forms the second dielectric layer selectively over the dielectric surface of the first dielectric layer. The dielectric material for the second dielectric layer may be deposited by performing, for example, a catalytic decomposition of a precursor gas in a surface reaction where the catalyst is obtained from the selectively formed metal-containing layer.

Processing methods may be performed to produce semiconductor structures. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.

The present disclosure provides a DNA-targeting RNA that comprises a targeting sequence and, together with a modifying polypeptide, provides for site-specific modification of a target DNA and/or a polypeptide associated with the target DNA. The present disclosure further provides site-specific modifying polypeptides. The present disclosure further provides methods of site-specific modification of a target DNA and/or a polypeptide associated with the target DNA The present disclosure provides methods of modulating transcription of a target nucleic acid in a target cell, generally involving contacting the target nucleic acid with an enzymatically inactive Cas9 polypeptide and a DNA-targeting RNA. Kits and compositions for carrying out the methods are also provided. The present disclosure provides genetically modified cells that produce Cas9; and Cas9 transgenic non-human multicellular organisms.

An object of the present invention is to provide a technique suitable for achieving low wiring resistance and reducing a variation in the resistance value between semiconductor elements to be multilayered in a method of manufacturing a semiconductor device in which the semiconductor elements are multilayered through laminating semiconductor wafers via an adhesive layer. The method of the present invention includes first to third processes. In the first process, a wafer laminate Y is prepared, the wafer laminate Y having a laminated structure including a wafer 3, wafers 1T with a thickness from 1 to 20 um, and an adhesive layer 4 with a thickness from 0.5 to 4.5 μm interposed between a main surface 3a of the wafer 3 and a back surface 1b of the wafer 1T. In the second process, holes extending from the main surface 1a of the wafer 1T and reaching a wiring pattern of the wafer 3 are formed by a predetermined etching treatment. In the third process, the holes are filled with a conductive material to form through electrodes. The adhesive layer 4 has an etching rate of 1 to 2 μm/min in dry etching performed using an etching gas containing CF.sub.4, O.sub.2, and Ar at a volume ratio of 100:400:200 under predetermined conditions.

An intermediate structure for forming a semiconductor device and method of making is provided. The intermediate device includes (i) a substrate comprising a Ga-based layer, and (ii) optionally, a metal layer on the substrate; wherein at least one of the Ga-based layer and, if present, the metal layer comprises at least a surface region having an isoelectric point of less than 7, usually at most 6.

A treatment, structure and system are provided that modify the deposition process of a material that can occur over two differing materials. In an embodiment the deposition rates may be adjusted by the treatment to change the deposition rate of one of the materials to be more in line with the deposition rate of a second one of the materials. Also, the deposition rates may be modified to be different from each other, to allow for a more selective deposition over the first one of the materials than over the second one of the materials.

There is provided a technique that includes: (a) modifying a surface of one base among a first base and a second base to be F-terminated by supplying a fluorine-containing radical generated from a fluorine-containing gas to a substrate where the first base and the second base are exposed at a surface of the substrate; and (b) forming a film on a surface of the other base, which is different from the one base, among the first base and the second base by supplying a film-forming gas to the substrate after modifying the surface of the one base.

A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.

There is provided a technique that includes a first opening and a second opening which supply gases to a process chamber in which a substrate is arranged, and is configured such that: the first opening and the second opening are arranged in a direction parallel to a surface of the substrate, a gas supplied from the first opening is supplied toward a center of the substrate, a gas supplied from the second opening is supplied toward a peripheral edge of the substrate, and a direction of the gas supplied from the second opening forms a predetermined angle with respect to a direction of the gas supplied from the first opening.