A semiconductor device and method of manufacture are provided. In some embodiments a divergent ion beam is utilized to implant ions into a capping layer, wherein the capping layer is located over a first metal layer, a dielectric layer, and an interfacial layer over a semiconductor fin. The ions are then driven from the capping layer into one or more of the first metal layer, the dielectric layer, and the interfacial layer.

Embodiments of the present disclosure generally relate to techniques for deposition of high-density films for patterning applications. In one embodiment, a method of processing a substrate is provided. The method includes depositing a carbon hardmask over a film stack formed on a substrate, wherein the substrate is positioned on an electrostatic chuck disposed in a process chamber, implanting ions into the carbon hardmask, wherein depositing the carbon hardmask and implanting ions into the carbon hardmask are performed in the same process chamber, and repeating depositing the carbon hardmask and implanting ions into the carbon hardmask in a cyclic fashion until a pre-determined thickness of the carbon hardmask is reached.

Various embodiments include methods to produce low dielectric-constant (low-k) films. In one embodiment, alternating ALD cycles and dopant materials are used to generate a new family of silicon low-k materials. Specifically, these materials were developed to fill high-aspect-ratio structures with re-entrant features. However, such films are also useful in blanket applications where conformal nanolaminates are applicable. Various embodiments also disclose SiOF as well as SiOCF, SiONF, GeOCF, and GeOF. Analogous films may include halide derivatives with iodine and bromine (e.g., replace “F” with “I” or “Br”). Other methods, chemistries, and techniques are disclosed.

A semiconductor device include a substrate including a peripheral region, a first active pattern provided on the peripheral region of the substrate, the first active pattern having an upper portion including first semiconductor patterns and second semiconductor patterns which are alternately stacked, a first gate electrode intersecting the first active pattern, a pair of first source/drain patterns provided at both sides of the first gate electrode, respectively, and a first gate insulating layer disposed between the first gate electrode and the first active pattern. The first gate insulating layer includes a first insulating layer formed on the first active pattern, a second insulating layer formed on the first insulating layer, and a high-k dielectric layer formed on the second insulating layer. The first gate insulating layer contains a first dipole element including lanthanum (La), aluminum (Al), or a combination thereof.

Improved methods are provided for transferring a photoresist pattern onto one or more underlying layers. In the disclosed embodiments, etch selectivity between a photoresist layer and one or more underlying layers is improved by pre-treating the underlying layer(s) with a plasma before the photoresist layer is deposited and patterned to form a photoresist pattern. The plasma modifies the underlying layer(s) by implanting ions into the underlying layer(s) to form a modified layer. When the modified layer is subsequently etched to transfer the photoresist pattern onto the modified layer, the presence of ions within the modified layer increases the etch rate of the modified layer, compared to the etch rate that the underlying layer(s) would have exhibited without plasma pre-treatment. The increased etch rate of the modified layer improves etch selectivity between the photoresist layer and the modified layer and mitigates defects during the photoresist pattern transfer process.

A semiconductor device includes a semiconductor-on-insulator water having a buried layer. The buried layer includes therein opposing etch barrier regions and a gate region between the etch barrier regions. The semiconductor device further includes at least one nanowire having a channel portion interposed between opposing source/drain portions. The channel portion is suspended in the gate region. A gate electrode is formed in the gate region, and completely surrounds all surfaces of the suspended nanowire. The buried layer comprises a first electrical insulating material, and the etch barrier regions comprising a second electrical insulating material different from the first electrical insulating material.

A method is provided for depositing a planarization layer over features on a substrate using sequential polymerization chemical vapor deposition. According to one embodiment, the method includes providing a substrate containing a plurality of features with gaps between the plurality of features, delivering precursor molecules by gas phase exposure to the substrate, adsorbing the precursor molecules on the substrate to at least substantially fill the gaps with a layer of the adsorbed precursor molecules, and reacting the precursor molecules to form a polymer layer that at least substantially fills the gaps.

There is provided a method of forming an etching-purpose mask structure on an insulating film containing silicon and oxygen, which includes: forming an intermediate film containing silicon, carbon, nitrogen and hydrogen as main components by supplying a first process gas onto the insulating film formed on a substrate; and subsequently, forming a tungsten film by supplying a second process gas containing a compound of tungsten to the substrate to replace some of silicon constituting the intermediate film with tungsten.

According to one embodiment, a method of manufacturing a semiconductor device comprises forming an oxide semiconductor layer, forming a gate insulating layer in contact with the oxide semiconductor layer and covering the oxide semiconductor layer, and forming a gate electrode on the gate insulating layer so as to overlap the oxide semiconductor layer, and injecting boron through the gate electrode and the gate insulating layer after forming the gate electrode, wherein a boron concentration included in a region of the gate insulating layer overlapping the gate electrode is in a range of 1E+16 [atoms/cm.sup.3] or more.

Disclosed are methods for etching a silicon-containing film to form a patterned structure, methods for reinforcing and/or strengthening and/or minimizing damage of a patterned mask layer while forming a patterned structure and methods for increasing etch resistance of a patterned mask layer in a process of forming a patterned structure. The methods include using an activated iodine-containing etching compound having the formula C.sub.nH.sub.xF.sub.yI.sub.z, wherein 4≤n≤10, 0≤x≤21, 0≤y≤21, and 1≤z≤4 as an etching gas. The activated iodine-containing etching compound produces iodine ions, which are implanted into the patterned hardmask layer, thereby strengthening the patterned mask layer.