A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.

A method includes forming a silicon layer on a wafer, forming an oxide layer in contact with the silicon layer, and, after the oxide layer is formed, annealing the wafer in an environment comprising ammonia (NH.sub.3) to form a dielectric barrier layer between, and in contact with, the silicon layer and the oxide layer. The dielectric barrier layer comprises silicon and nitrogen.

Various aspects relate to a functional layer and the formation thereof. A method for manufacturing a functional layer of an electronic device may include: forming a plurality of sublayers of the functional layer by a plurality of consecutive sublayer processes, each sublayer process of the plurality of consecutive sublayer processes comprising: forming a sublayer of the plurality of sublayers by vapor deposition, the sublayer comprising one or more materials, and, subsequently, crystallizing the one or more materials comprised in the sublayer.

A transistor device that includes a single semiconductor structure having an outer perimeter and a vertical height, wherein the single semiconductor structure is at least partially defined by a trench formed in a semiconductor substrate and a first layer of material positioned on the bottom surface of the trench and around the outer perimeter of the single semiconductor structure. The device also includes a second layer of material positioned on the first layer of material and around the outer perimeter of the single semiconductor structure, a gap between the outer perimeter of the single semiconductor structure and both the first and second layers of material (when considered collectively) and an insulating sidewall spacer positioned in the gap, wherein the insulating sidewall spacer has a vertical height that is less than the vertical height of the single semiconductor structure.

A semiconductor device including a first dielectric layer and a second dielectric layer is formed by forming an inhibitor layer over a semiconductor material. The inhibitor layer includes at least silicon and nitrogen. The semiconductor material is heated in an oxygen-containing ambient which oxidizes the inhibitor layer and forms the first dielectric layer which includes the oxidized inhibitor layer, and oxidizes the semiconductor material to form the second dielectric layer. The second dielectric layer is thicker than, the first dielectric layer. The first dielectric layer and the second dielectric layer each include at least 90 weight percent silicon dioxide and less than 1 weight percent nitrogen. The first dielectric layer and the second dielectric layer may be used to form gate dielectric layers for a first MOS transistor and a second MOS transistor that operates at a higher voltage than the first MOS transistor.

An apparatus for treating a substrate, the apparatus comprising: a processing container having an inner space; a support unit having a support plate configured to support and rotate the substrate in the inner space; a liquid supply unit supplying treating liquid to the substrate supported by the support unit; and an exhaust unit exhausting an air flow in the inner space, wherein the processing container includes a bottom wall and a side wall extending from the outside end of the bottom wall, the processing container including a first gas-liquid separator provided at the side wall.

The embodiments of mechanisms for doping wells of finFET devices described in this disclosure utilize depositing doped films to dope well regions. The mechanisms enable maintaining low dopant concentration in the channel regions next to the doped well regions. As a result, transistor performance can be greatly improved. The mechanisms involve depositing doped films prior to forming isolation structures for transistors. The dopants in the doped films are used to dope the well regions near fins. The isolation structures are filled with a flowable dielectric material, which is converted to silicon oxide with the usage of microwave anneal. The microwave anneal enables conversion of the flowable dielectric material to silicon oxide without causing dopant diffusion. Additional well implants may be performed to form deep wells. Microwave anneal(s) may be used to anneal defects in the substrate and fins.

In accordance with an embodiment of the present invention, a method of forming a densified fill layer is provided. The method includes forming a pair of adjacent vertical fins on a substrate, forming an inner liner on the sidewalls of the adjacent vertical fins, and forming a sacrificial layer on the inner liner. The method further includes forming a fill layer between the pair of adjacent vertical fins, wherein the fill layer is in contact with at least a portion of the sacrificial layer, removing at least a portion of the sacrificial layer in contact with the fill layer to form sidewall channels adjacent to the fill layer, and subjecting the fill layer to a densification process to form the densified fill layer.

A composition and method for using the composition in the fabrication of an electronic device are disclosed. Compounds, compositions and methods for depositing a low dielectric constant (<4.0) and high oxygen ash resistance silicon-containing film such as, without limitation, a carbon doped silicon oxide, are disclosed.

A Si-containing film forming composition comprising a catalyst and/or a polysilane and a N—H free, C-free, and Si-rich perhydropolysilazane having a molecular weight ranging from approximately 332 dalton to approximately 100,000 dalton and comprising N—H free repeating units having the formula [—N(SiH3)x(SiH2-)y], wherein x=0, 1, or 2 and y=0, 1, or 2 with x+y=2; and x=0, 1 or 2 and y=1, 2, or 3 with x+y=3. Also disclosed are synthesis methods and applications for using the same.