The present disclosure describes a semiconductor structure having bonded wafers with storage layers and a method to bond wafers with storage layers. The semiconductor structure includes a first wafer including a first storage layer with carbon, a second wafer including a second storage layer with carbon, and a bonding layer interposed between the first and second wafers and in contact with the first and second storage layers.

A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Embodiments of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the embodiments described herein provide techniques for depositing nitrogen-doped diamond-like carbon films for patterning applications. In one or more embodiments, a method for processing a substrate includes flowing a deposition gas containing a hydrocarbon compound and a nitrogen dopant compound into a processing volume of a process chamber having a substrate positioned on an electrostatic chuck, and generating a plasma at or above the substrate by applying a first RF bias to the electrostatic chuck to deposit a nitrogen-doped diamond-like carbon film on the substrate. The nitrogen-doped diamond-like carbon film has a density of greater than 1.5 g/cc and a compressive stress of about −20 MPa to less than −600 MPa.

Semiconductor devices and methods of manufacturing are presented in which a first spacer layer and a second spacer layer are formed. In embodiments the first spacer layer and the second spacer layer are formed with an enhanced etch resistance. Such an enhanced etch resistance works to help prevent undesired breakthroughs during subsequent manufacturing processes.

A method for shallow trench isolation structures in a semiconductor device and a semiconductor device including the shallow trench isolation structures are disclosed. In an embodiment, the method may include forming a trench in a substrate; depositing a first dielectric liner in the trench; depositing a first shallow trench isolation (STI) material over the first dielectric liner, the first STI material being deposited as a conformal layer; etching the first STI material; depositing a second STI material over the first STI material, the second STI material being deposited as a flowable material; and planarizing the second STI material such that top surfaces of the second STI material are co-planar with top surfaces of the substrate.

A semiconductor device with a small variation in transistor characteristics is provided. The semiconductor device includes an oxide semiconductor film, a source electrode and a drain electrode over the oxide semiconductor film, an interlayer insulating film placed to cover the oxide semiconductor film, the source electrode, and the drain electrode, a first gate insulating film over the oxide semiconductor film, a second gate insulating film over the first gate insulating film, and a gate electrode over the second gate insulating film. The interlayer insulating film has an opening overlapping with a region between the source electrode and the drain electrode, the first gate insulating film, the second gate insulating film, and the gate electrode are placed in the opening of the interlayer insulating film, the first gate insulating film includes oxygen and aluminum, and the first gate insulating film includes a region thinner that is than the second gate insulating film.

An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.

Described herein is a technique capable of acquiring, monitoring and recording the progress of the reaction between a substrate and a reactive gas contained in a process gas in a process chamber during the processing of the substrate. According to the technique, there is provided a substrate processing apparatus including: a process chamber accommodating a substrate; a process gas supply system configured to supply a process gas into the process chamber via a process gas supply pipe; an exhaust pipe configured to exhaust an inner atmosphere of the process chamber; a first gas concentration sensor configured to detect a first concentration of a reactive gas contained in the process gas in the process gas supply pipe; and a second gas concentration sensor configured to detect a second concentration of the reactive gas contained in an exhaust gas in the exhaust pipe.

A semiconductor device structure and methods of forming the same are described. In some embodiments, the method includes forming a dielectric layer, which includes forming an as deposited layer using an atomic layer deposition process, which includes flowing a silicon source precursor into a process chamber at a first flow rate, flowing a carbon and nitrogen source precursor into the process chamber at a second flow rate, and flowing an oxygen source precursor into the process chamber at a third flow rate. A ratio of the first flow rate to the second flow rate to the third flow rate ranges between about one to one to eight and one to one to twelve, and the as deposited layer has a carbon concentration substantially greater than a nitrogen concentration. The method further includes annealing the as deposited layer in an environment including H.sub.2O to form the dielectric layer.

Chalcogen silane precursors are described. Methods for depositing a silicon nitride (Si.sub.xN.sub.y) film on a substrate are described. The substrate is exposed to the chalcogen silane and a reactant to deposit the silicon nitride (Si.sub.xN.sub.y) film. The exposures can be sequential or simultaneous. The chalcogen silane may be substantially free of halogen. The chalcogen may be selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te).