Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

A substrate processing method includes holding a substrate on which a boron-containing silicon film is formed; supplying an oxidative aqueous solution including hydrofluoric acid and nitric acid to the held substrate; and etching the boron-containing silicon film of the substrate with the oxidative aqueous solution.

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer, a source/drain structure, a contact structure, a glue layer and a barrier layer. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The contact structure is positioned over the source/drain structure. The glue layer covers a bottom surface and a sidewall surface of the contact structure. The barrier layer encircles the sidewall surface of the contact structure. A bottom surface of the glue layer is exposed to the barrier layer.

A method of forming a crystalline semiconductor material on the basis of a very thin semiconductor base material and an amorphous semiconductor material deposited thereon is disclosed. Radiation-based anneal process techniques may be applied by using appropriate radiation wavelengths, for instance, below 380 nm, in order to efficiently restrict energy deposition to the surface-near area. A solid and crystalline bottom portion of the semiconductor base material may be reliably preserved, thereby achieving crystallization of the overlying material portions and, in particular, of the previously deposited amorphous semiconductor material. Extremely thin channel regions of fully depleted SOI transistor elements may be used as a semiconductor base material, upon which raised drain and source regions may be formed in a later manufacturing stage, thereby substantially avoiding any process irregularities, which are conventionally associated with the epitaxial growth of a semiconductor material on a very thin semiconductor base material.

The present disclosure generally relates to apparatus and methods for forming a low-k dielectric material on a substrate. The method includes various substrate processing steps utilizing a wet processing chamber, a solvent exchange chamber, and a supercritical fluid chamber. More specifically, a dielectric material in an aqueous solution may be deposited on the substrate and a solvent exchange process may be performed to prepare the substrate for a supercritical drying process. During the supercritical drying process, liquids present in the solution and remaining on the substrate from the solvent exchange process are removed via sublimation during the supercritical drying process. The resulting dielectric material formed on the substrate may be considered a silica aerogel which exhibits a very low k-value.

A method of forming a crystalline semiconductor material on the basis of a very thin semiconductor base material and an amorphous semiconductor material deposited thereon is disclosed. Radiation-based anneal process techniques may be applied by using appropriate radiation wavelengths, for instance, below 380 nm, in order to efficiently restrict energy deposition to the surface-near area. A solid and crystalline bottom portion of the semiconductor base material may be reliably preserved, thereby achieving crystallization of the overlying material portions and, in particular, of the previously deposited amorphous semiconductor material. Extremely thin channel regions of fully depleted SOI transistor elements may be used as a semiconductor base material, upon which raised drain and source regions may be formed in a later manufacturing stage, thereby substantially avoiding any process irregularities, which are conventionally associated with the epitaxial growth of a semiconductor material on a very thin semiconductor base material.

A substrate processing apparatus includes a periphery removal unit configured to remove a peripheral portion of a film formed on a surface of a substrate; a profile acquisition unit configured to acquire a removal width profile indicating a relationship between a position in a circumferential direction of the substrate and a width of a portion of the substrate from which the film is removed; and a factor estimation unit configured to output factor information indicating a factor of an error in the width based on the removal width profile.

Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

A field-effect transistor and a manufacturing method thereof are provided. The method includes depositing a first insulating layer on a substrate; forming a source electrode and a drain electrode on the first insulating layer; forming a carbon quantum dots active layer covering the source electrode and the drain electrode; and forming a second insulating layer and a gate electrode on the carbon quantum dots active layer sequentially. According to the above method, the present disclosure making the field-effect transistor active layer with carbon quantum dots as materials, which enriches the material of the field-effect transistor, reduces the environmental pollution in current technology by using metal dots film, and reduces the dependence on metal elements.