Provided is a semiconductor device including: a gate electrode; a channel layer arranged in a region directly below or directly above the gate electrode; a source and a drain electrodes arranged to be in contact with the channel layer; and a first insulating layer arranged between the gate electrode and the channel layer, the channel layer including a first oxide semiconductor, the source electrode and/or the drain electrode including a second oxide semiconductor, the first and second oxide semiconductors containing In, W and Zn, a content rate of W/(In+W+Zn) being higher than 0.001 atomic % and not higher than 8.0 atomic %, a content rate of Zn/(In+W+Zn) being from 1.2 atomic % to 40 atomic %, an atomic ratio of Zn to W being higher than 1.0 and lower than 20000. Also provided is a method for manufacturing the device.

Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.

Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.

A method of manufacturing a memory device including following steps is provided. A first dielectric layer and a first conductive layer are formed in order on the substrate. A first opening and a second opening on the first opening are formed in the substrate, the first dielectric layer and the first conductive layer. An isolation structure is formed in the first opening. A second dielectric layer is formed on the substrate to conformally cover a top surface of the first conductive layer and a surface of the second opening. A heat treatment is performed on the second dielectric layer to enhance the bonding between the second dielectric layer and the first conductive layer. An etching process is performed, so as to remove a portion of the second dielectric layer and expose a top surface of the isolation structure.

The present invention is broadly concerned with materials, processes, and structures that allow an underlayer to be imaged directly using conventional lithography, thus avoiding the photoresist processing steps required by prior art directed self-assembly (DSA) processes. The underlayers can be tailored to favor a selected block of the DSA block co-polymers (BCP), depending on the pattern, and can be formulated either to initially be neutral to the BCP and switch to non-neutral after photoexposure, or can initially be non-neutral to the BCP and switch to neutral after exposure. These materials allow fast crosslinking to achieve solvent resistance and possess good thermal stability.

A substrate on which a processing film made of a directed self-assembly material is formed is placed on a holding plate incorporating a preheating mechanism, and is preheated. A low oxygen atmosphere surrounds the substrate. A preheating temperature is a temperature at which the directed self-assembly material comprised of two types of polymers is phase-separated. By preheating the processing film, the two types of polymers are phase-separated to form a fine pattern. The processing film is irradiated with flashes of light from flash lamps while being preheated. This increases the fluidity of the polymers constituting the processing film to achieve the formation of a fine pattern while suppressing the occurrence of defects.

Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.

The present invention provides a manufacturing method of an OLED display panel, including frosting a portion of an inner surface of an encapsulation cover plate corresponding to both sides of a glass frit to-be-disposed region; disposing a light shielding film at the frosted treatment region of the inner surface of the encapsulation cover plate, wherein the light shielding film is a metal film having a light transmittance less than a first predetermined value or a non-metal film having a light transmittance less than a second predetermined value; and disposing a glass frit on the glass frit to-be-disposed region.

In-situ formation of a block copolymer through deprotection can provide patterns with flexible pitches. A layer of a protected polymer including a protecting group is formed. One or more portions of the layer may be exposed to light. The exposed portion(s) may be baked after the light exposure. The protecting group is removed after the light exposure or bake so that the protected polymer becomes a deprotected polymer in the exposure portion(s). The deprotected polymer is bonded with the protected polymer in the unexposed portion(s) of the layer but has a different solubility from the protected polymer so that phases of the block copolymer are separated. The phase separation can provide a periodic pattern with various pitches. The solution and roughness of the pattern can be enhanced by using CARs formed with a protected, cross-linked polymer that includes a protective group and a function group with a ratio of 50:50.