A gate insulator film made of silicon dioxide or gallium oxide is formed on a gallium nitride (GaN) substrate. The GaN substrate is preheated by irradiation with light from halogen lamps, and the surface of the substrate including the gate insulator film is heated to a high temperature for an extremely short time by irradiation with a flash of light from flash lamps. Heating the substrate surface including the gate insulator film in an extremely short heat treatment time prevents the desorption of nitrogen from GaN and makes it possible to reduce the traps existing at the interface between the gate insulator film and GaN without diffusing gallium into the gate insulator film.

There is provided a technique that includes: (a) forming a first film containing boron and at least first bonds selected from the group of Si—C bonds and Si—N bonds on a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a boron-containing pseudo-catalyst gas to the substrate; and supplying a first precursor gas containing at least the first bonds selected from the group of the Si—C bonds and the Si—N bonds to the substrate; (b) modifying the first film to a second film by supplying a gas containing hydrogen and oxygen to the substrate; and (c) modifying the second film to a third film by performing a thermal annealing process to the second film.

Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

A heterojunction device is provided. The heterojunction device includes a silicon (Si) substrate; and a film of silicon carbide (SiC) deposited on a surface of the Si substrate. The SiC has a Si:C ratio that increases or decreases from a SiC surface in contact with the Si substrate to an opposing SiC surface that is not in contact with the Si substrate.

According to a flexible light-emitting device production method of the present disclosure, after an intermediate region (30i) and flexible substrate regions (30d) of a plastic film (30) of a multilayer stack (100) are divided from one another, the interface between the flexible substrate regions (30d) and a glass base (10) is irradiated with lift-off light. The multilayer stack (100) is separated into a first portion (110) and a second portion (120) while the multilayer stack (100) is in contact with a stage (210). The first portion (110) includes a plurality of light-emitting devices (1000) which are in contact with the stage (210). The light-emitting devices (1000) include a plurality of functional layer regions (20) and the flexible substrate regions (30d). The second portion (120) includes the glass base (10) and the intermediate region (30i). The step of irradiating with the lift-off light includes making the irradiation intensity of lift-off light for at least part of the interface between the intermediate region (30i) and the glass base (10) lower than the irradiation intensity of lift-off light for the interface between the flexible substrate regions (30d) and the glass base (10).

Methods and systems for forming a structure including a dielectric material layer on a surface of a substrate and structures and devices formed using the method or system are disclosed. Exemplary methods include providing a substrate within a reaction chamber of a reactor system, providing one or more precursors to the reaction chamber, and providing pulsed plasma power to polymerize the one or more precursors within the reaction chamber.

Embodiments described herein generally related to methods for forming a flowable low-k dielectric layer over a trench formed on a surface of a patterned substrate. The methods include delivering a silicon and carbon containing precursor into a substrate processing region of a substrate processing chamber for a first period of time and a second period of time, flowing an oxygen-containing precursor into a remote plasma region of a plasma source while igniting a remote plasma to form a radical-oxygen precursor, flowing the radical-oxygen precursor into the substrate processing region at a second flow rate after the first period of time has elapsed and during the second period of time, and exposing the silicon and carbon containing dielectric precursor to electromagnetic radiation for a third period of time after the second period of time has elapsed.

Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

Provided is a semiconductor device including: a gate electrode; a channel layer arranged in a region directly below or directly above the gate electrode; a source and a drain electrodes arranged to be in contact with the channel layer; and a first insulating layer arranged between the gate electrode and the channel layer, the channel layer including a first oxide semiconductor, the source electrode and/or the drain electrode including a second oxide semiconductor, the first and second oxide semiconductors containing In, W and Zn, a content rate of W/(In+W+Zn) being higher than 0.001 atomic % and not higher than 8.0 atomic %, a content rate of Zn/(In+W+Zn) being from 1.2 atomic % to 40 atomic %, an atomic ratio of Zn to W being higher than 1.0 and lower than 20000. Also provided is a method for manufacturing the device.