A method of fabricating semiconductor devices is provided. The method includes forming an interfacial layer on a substrate, and depositing a gate dielectric layer on the interfacial layer. The method also includes treating the gate dielectric layer with a first post deposition annealing (PDA) process. The method further includes depositing a first capping layer on the gate dielectric layer, and treating the gate dielectric layer by performing a post metal annealing (PMA) process on the first capping layer. In addition, the method includes removing the first capping layer, and treating the gate dielectric layer with a second PDA process. The method also includes forming a gate electrode layer on the gate dielectric layer.

A method for manufacturing a display module includes preparing a display module comprising a plurality of layers and forming a through-hole in the display module. The forming the through-hole includes performing a first irradiation process of irradiating a first laser beam along a first boundary defining the through-hole, performing a second irradiation process of irradiating a second laser beam along a second boundary after the first irradiation process, and performing a third irradiation process of irradiating a third laser beam along a third boundary after the second irradiation process. A time interval between the first irradiation process and the second irradiation process may be different from a time interval between the second irradiation process and the third irradiation process.

A substrate processing method for forming a nitride film on a substrate, includes: a raw material gas supply step of supplying a raw material gas containing an element to be nitrided; a hydrogen gas supply step of, after the raw material gas supply step, supplying a hydrogen gas activated by plasma; a thermal nitriding step of supplying a first nitriding gas containing nitrogen activated by heat and nitriding the element; and a plasma nitriding step of supplying a second nitriding gas containing nitrogen activated by plasma and nitriding the element.

Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with dielectric material comprising silicon, oxygen and carbon. The carbon is present to a concentration within a range of from about 3 atomic percent to about 20 atomic percent. Some embodiments include a method of providing dielectric fill across a semiconductor construction having an opening extending therein. The semiconductor construction has an upper surface proximate the opening. The method includes forming photopatternable dielectric material within the opening and across the upper surface, and exposing the photopatternable dielectric material to patterned actinic radiation. Subsequently, the photopatternable dielectric material is developed to pattern the photopatternable dielectric material into a first dielectric structure which at least partially fills the opening, and to remove the photopatternable dielectric material from over the upper surface.

A true random number generator including a transistor, a first voltage source, a second voltage source, and a comparator. The transistor has a first electrode, a second electrode, and a third electrode. Two of the electrodes are electrically connected by a channel of conductive nanomaterial. The first voltage source is electrically connected to the first electrode and the second voltage source is electrically connected to the second electrode. The comparator is electrically connected to the third electrode and is configured to classify a measured electrical property at the third electrode as either HIGH or LOW based on a comparison of the measured electrical property with a reference value. The measured electrical property varies over time due to random telegraph signals (RTSs) due to defects in the transistor.

A method of fabricating semiconductor devices is provided. The method includes forming an interfacial layer on a substrate, and depositing a gate dielectric layer on the interfacial layer. The method also includes treating the gate dielectric layer with a first post deposition annealing (PDA) process. The method further includes depositing a first capping layer on the gate dielectric layer, and treating the gate dielectric layer by performing a post metal annealing (PMA) process on the first capping layer. In addition, the method includes removing the first capping layer, and treating the gate dielectric layer with a second PDA process. The method also includes forming a gate electrode layer on the gate dielectric layer.

To allow a metal oxide film composed mainly of O and at least one of Hf and Zr to exhibit ferroelectric properties. After deposition of a hafnium oxide film on a semiconductor substrate via an insulating film, the semiconductor substrate is exposed to microwaves to selectively heat the hafnium oxide film. This makes it possible to form a larger number of orthorhombic crystals in the crystals of the hafnium oxide film. The hafnium oxide film thus obtained can therefore exhibit ferroelectric properties without adding, thereto, an impurity such as Si. This means that the hafnium oxide film having a reverse size effect can be used as a ferroelectric film of a ferroelectric memory cell and contributes to the manufacture of a miniaturized ferroelectric memory cell.

A process for manufacturing interconnect BEOL structures from a patternable low-k dielectric on a microcircuit substrate having an optional anti-reflective coating comprises applying to the microcircuit substrate a via coating for forming a via comprising a low-k patternable dielectric coating, exposing the via coating to a via pattern, developing the exposed via coating, curing the exposed and developed via coating to form a via film, applying a trench coating for forming a trench comprising a patternable low-k dielectric coating, exposing the trench coating to a trench pattern, developing the exposed and developed trench coating, followed by curing the trench coating to form a trench film; Curing one of the uncured coatings to form a film prevents it from inter-mixing with the other applied uncured coating. Articles of manufacture comprise products made by this process as well as dual-damascene integrated spun-on patterned low-k dielectrics, and single-damascene integrated spun-on patterned low-k dielectrics.

Embodiments described herein generally related to methods for forming a flowable low-k dielectric layer over a trench formed on a surface of a patterned substrate. The methods include delivering a silicon and carbon containing precursor into a substrate processing region of a substrate processing chamber for a first period of time and a second period of time, flowing an oxygen-containing precursor into a remote plasma region of a plasma source while igniting a remote plasma to form a radical-oxygen precursor, flowing the radical-oxygen precursor into the substrate processing region at a second flow rate after the first period of time has elapsed and during the second period of time, and exposing the silicon and carbon containing dielectric precursor to electromagnetic radiation for a third period of time after the second period of time has elapsed.

Pressure in a chamber receiving a semiconductor wafer is reduced to a level less than atmospheric pressure. The semiconductor wafer is subjected to heat treatment in a reduced-pressure atmosphere by being irradiated with a flash of light. A leak determination part determines that a leak occurs at the chamber if pressure in the chamber does not reach target pressure while a time period passed since start of reduction of pressure in the chamber exceeds a threshold set in advance. A leak at the chamber is detected by monitoring a time period passed since start of reduction of pressure in the chamber. This makes it possible to determine the presence or absence of a leak at the chamber with a simple structure without requiring installation of a new hardware structure.