The present disclosure provides a layering structure that permits integration of epitaxially oriented perovskite oxides, such as bismuth ferrite (BiFeO.sub.3), epitaxially oriented barium titanate (BaTiO.sub.3), epitaxially oriented (SrTiO.sub.3), or their superstructures (BTO/STO) or solid solutions, onto a Si substrate through a perovskite buffer layer. The structure can retain thermal process-sensitive dopant positions and other thermal process window-sensitive features through atomic layer deposition of an oxide perovskite. Also provided are methods of preparing these layered structures.

Examples of a technique for forming a dielectric material for an integrated circuit are provided herein. In an example, an integrated circuit workpiece is received that includes a recess. A first dielectric precursor is deposited in the recess. The first dielectric precursor includes a non-semiconductor component. A second dielectric precursor is deposited in the recess on the first dielectric precursor, and an annealing process is performed such that a portion of the non-semiconductor component of the first dielectric precursor diffuses into the second dielectric precursor. The non-semiconductor component may include oxygen, and the annealing process may be performed in one of a vacuum or an inert gas environment.

A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.

A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.

The present disclosure provides a semiconductor device and a method for forming a semiconductor device. The semiconductor device includes a substrate, and a first gate dielectric stack over the substrate, wherein the first gate dielectric stack includes a first ferroelectric layer, and a first dielectric layer coupled to the first ferroelectric layer, wherein the first ferroelectric layer includes a first portion made of a ferroelectric material in orthorhombic phase, a second portion made of the ferroelectric material in monoclinic phase, and a third portion made of the ferroelectric material in tetragonal phase, wherein a total volume of the second portion is greater than a total volume of the first portion and the total volume of the first portion is greater than a total volume of the third portion.

Systems, apparatuses, and methods related to semiconductor structure formation are described. An example apparatus includes a structural material for a semiconductor device. The structural material includes an orthosilicate derived oligomer having a number of oxygen (O) atoms each chemically bonded to one of a corresponding number of silicon (Si) atoms and a chemical bond formed between an element from group 13 of a periodic table of elements (e.g., B, Al, Ga, In, and Tl) and the number of O atoms of the orthosilicate derived oligomer. The chemical bond crosslinks chains of the orthosilicate derived oligomer to increase mechanical strength of the structural material, relative to the structural material formed without the chemical bond to crosslink the chains, among other benefits described herein.

Bilayer stack for a ferroelectric tunnel junction and method of forming. The method includes depositing a first metal oxide film on a substrate by performing a first plurality of cycles of atomic layer deposition, where the first metal oxide film contains hafnium oxide, zirconium oxide, or both hafnium oxide and zirconium oxide, depositing a second metal oxide film on the substrate by performing a second plurality of cycles of atomic layer deposition, where the second metal oxide film contains hafnium oxide and zirconium oxide, and has a different hafnium oxide and zirconium oxide content than the first metal oxide film, and heat-treating the substrate to form a ferroelectric phase in the second metal oxide film but not in the first metal oxide film. A ferroelectric tunnel junction includes a first metal-containing electrode, the first metal oxide film, the second metal oxide film, and a second metal-containing electrode.

A preparation method for the capacitor structure includes: forming a dielectric layer on a first electrode, wherein, the dielectric layer includes a first amorphous layer and a high dielectric constant layer which are stacked, the first amorphous layer maintaining an amorphous structure after annealing, and the high dielectric constant layer being formed by crystallizing an initial dielectric constant layer after annealing; and forming a second electrode on the dielectric layer. Since the first amorphous layer remains an amorphous structure after annealing, electron transport can be suppressed, thereby reducing the leakage current of the capacitor structure.

Provided is a storage device according to an embodiment including: a stacked body including gate electrode layers stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; and a gate insulating film provided between the semiconductor layer and the gate electrode layer, the gate insulating film having a first region disposed between the gate electrode layer and the semiconductor layer and a second region disposed between the two first regions adjacent to each other in the first direction, the gate insulating film containing a hafnium oxide, in which a first thickness of the first region in the second direction from the semiconductor layer toward the gate electrode layer is smaller than a second thickness of the second region in the second direction.

There is provided a substrate processing apparatus including: a processing container having a vacuum atmosphere formed therein; a stage provided within the processing container and configured to place a substrate on the stage; a film-forming gas supply part configured to supply a film-forming gas for forming an organic film on the substrate placed on the stage; and a heating part configured to heat the substrate placed on the stage in a non-contact manner so as to remove a surface portion of the organic film.