To allow a metal oxide film composed mainly of O and at least one of Hf and Zr to exhibit ferroelectric properties. After deposition of a hafnium oxide film on a semiconductor substrate via an insulating film, the semiconductor substrate is exposed to microwaves to selectively heat the hafnium oxide film. This makes it possible to form a larger number of orthorhombic crystals in the crystals of the hafnium oxide film. The hafnium oxide film thus obtained can therefore exhibit ferroelectric properties without adding, thereto, an impurity such as Si. This means that the hafnium oxide film having a reverse size effect can be used as a ferroelectric film of a ferroelectric memory cell and contributes to the manufacture of a miniaturized ferroelectric memory cell.

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.

In one aspect, the invention is formulations comprising both organoaminohafnium and organoaminosilane precursors that allows anchoring both silicon-containing fragments and hafnium-containing fragments onto a given surface having hydroxyl groups to deposit silicon doped hafnium oxide having a silicon doping level ranging from 0.5 to 8 mol %, preferably 2 to 6 mol %, most preferably 3 to 5 mol %, suitable as ferroelectric material. In another aspect, the invention is methods and systems for depositing the silicon doped hafnium oxide films using the formulations.

Gate fabrication techniques are disclosed herein for providing gate stacks and/or gate structures (e.g., high-k/metal gates) with improved profiles (e.g., minimal to no warping, bending, bowing, and necking and/or substantially vertical sidewalls), which may be implemented in various device types. For example, gate fabrication techniques disclosed herein provide gate stacks with stress-treated glue layers having a residual stress that is less than about 1.0 gigapascals (GPa) (e.g., about -2.5 GPa to about 0.8 GPa). In some embodiments, a stress-treated glue layer is provided by depositing a glue layer over a work function layer and performing a stress reduction treatment, such as an ion implantation process and/or an annealing process in a gas ambient, on the glue layer. In some embodiments, a stress-treated glue layer is provided by forming at least one glue sublayer/metal layer pair over a work function layer, performing a poisoning process, and forming a glue sublayer over the pair.

A method for shallow trench isolation structures in a semiconductor device and a semiconductor device including the shallow trench isolation structures are disclosed. In an embodiment, the method may include forming a trench in a substrate; depositing a first dielectric liner in the trench; depositing a first shallow trench isolation (STI) material over the first dielectric liner, the first STI material being deposited as a conformal layer; etching the first STI material; depositing a second STI material over the first STI material, the second STI material being deposited as a flowable material; and planarizing the second STI material such that top surfaces of the second STI material are co-planar with top surfaces of the substrate.

A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.

Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp.sup.2 bonding structure.

A method of producing an inorganic solid pattern is described that includes: a step of coating an inorganic solid with a composition containing a polymetalloxane and an organic solvent; a step of heating the coating film obtained in the coating step, at a temperature of 100° C. or more and 1000° C. or less to form a heat-treated film; a step of forming a pattern of the heat-treated film; and a step of patterning the inorganic solid by etching using the pattern of the heat-treated film as a mask.

The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the device includes a substrate with fins thereon; an interfacial layer on the fins; a crystallized ferroelectric layer on the interfacial layer; and a metal gate layer on the ferroelectric layer.

A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1 × 10.sup.21 cm.sup.-3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1 × 10.sup.18 cm.sup.-3 and a carbon concentration at the first position is equal to or less than 1 × 10.sup.18 cm.sup.-3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1 × 10.sup.18 cm-.sup.3.