An electronic device with improved variable resistance characteristics and a method for fabricating the same are provided. In an embodiment of the disclosed technology, a method for forming an electronic device with a semiconductor memory includes forming a crystalized doped layer over a substrate; forming a barrier layer over the doped layer; forming a metal layer over the barrier layer; and reacting the barrier layer with a portion of the metal layer. The electronic device and the method of fabricating the same according to embodiments of the disclosed technology may have improved variable resistance characteristics.

Provided are a film structure including hafnium oxide, an electronic device including the same, and a method of manufacturing the same. The film structure including hafnium oxide includes a hafnium oxide layer including hafnium oxide crystallized in a tetragonal phase, and first and second stressor layers apart from each other with the hafnium oxide layer therebetween and applying compressive stress to the hafnium oxide layer.

The present disclosure provides a semiconductor device, including a substrate, a metal gate layer over the substrate, a channel between a source region and a drain region in the substrate, and a ferroelectric layer between the metal gate layer and the substrate, wherein the ferroelectric layer is configured to cause a strain in the channel when applied with an electrical field.

Dielectric films for semiconductor devices and methods of forming. A processing method includes forming a first film of a first dielectric material on a substrate by performing a first plurality of cycles of atomic layer deposition and, thereafter, heat-treating the first film, where a thickness of the first film is below a threshold thickness needed for spontaneous polarization in the first dielectric material. The processing method further includes forming a second film of a second dielectric material on the substrate by performing a second plurality of cycles of atomic layer deposition and, thereafter, heat-treating the second film, where a thickness of the second film is greater than the thickness of the first film, and the second film is ferroelectric or antiferroelectric. The first and second dielectric materials can include at least one metal oxide, for example zirconium oxide, hafnium oxide, or a laminate or mixture thereof.

Artificial synaptic devices with an HfO.sub.2-based ferroelectric layer that can be implemented in the CMOS back-end are provided. In one aspect, an artificial synapse element is provided. The artificial synapse element includes: a bottom electrode; a ferroelectric layer disposed on the bottom electrode, wherein the ferroelectric layer includes an HfO.sub.2-based material that crystallizes in a ferroelectric phase at a temperature of less than or equal to about 400° C.; and a top electrode disposed on the bottom electrode. An artificial synaptic device including the present artificial synapse element and methods for formation thereof are also provided.

A semiconductor structure includes a semiconductor substrate, n-type and p-type FinFETs on the substrate, each of the n-type and the p-type FinFETs include a channel region and a gate structure surrounding the channel region, each gate structure having a phase-changed high-k gate dielectric layer lining a gate trench thereof, the gate trench defined by a pair of spacers. The semiconductor structure further includes a conformal dielectric capping layer over each phase-changed high-k gate dielectric layer, the conformal dielectric capping layer having a higher dielectric constant than the phase-changed high-k gate dielectric layer. Further included on the n-type FinFETs is a multi-layer replacement gate stack of n-type work function material over the phase-changed high-k gate dielectric layer. A method of fabricating the semiconductor structure is also provided.

In a method of manufacturing a circuit including a MOSFET disposed in a MOSFET region and a negative capacitance FET (NCFET) disposed in a NCFET region, a dielectric layer is formed over a channel layer in the MOSFET region and the NCFET region. A first metallic layer is formed over the dielectric layer in the MOSFET region and the NCFET region. After the first metallic layer is formed, an annealing operation is performed only in the NCFET region. After the annealing operation, the first metallic layer is removed from the MOSFET region and the NCFET region. The annealing operation includes irradiating the first metallic layer and the dielectric layer in the NCFET region with an energy beam.

A heating device for heating the surface of a substrate. The heating device comprises a gas source comprising an inert material supply inert under the operating conditions of the heating device, the gas source being adapted for supplying a hot jet of a gas comprising at least elements of said inert material on the substrate. The gas source is adapted for heating the hot jet of the gas to a temperature above 1500° C.

Provided are an electronic device including a dielectric layer having an adjusted crystal orientation and a method of manufacturing the electronic device. The electronic device includes a seed layer provided on a substrate and a dielectric layer provided on the seed layer. The seed layer includes crystal grains having aligned crystal orientations. The dielectric layer includes crystal grains having crystal orientations aligned in the same direction as the crystal orientations of the seed layer.

A method of manufacturing a semiconductor device includes a first laminating step, a second laminating step, a third laminating step, a first annealing step, and a fourth laminating step. In the first laminating step, a first electrode film is laminated on a substrate. In the second laminating step, a capacitive insulator is laminated on the first electrode film. In the third laminating step, a metal oxide is laminated on the capacitive insulator. In the first annealing step, the first electrode film, the capacitive insulator, and the metal oxide, which are laminated on the substrate, are annealed. In the fourth laminating step, a second electrode film is laminated on the annealed metal oxide. The capacitive insulator is an oxide that contains at least one of zirconium and hafnium, and the metal oxide is an oxide that contains at least one of tungsten, molybdenum, and vanadium.