Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer.

A flash memory is provided and includes a substrate including a memory cell region; a memory transistor array including memory transistors and selecting transistors in the memory cell region; a functional layer covering outer surfaces of the memory transistors and selecting transistors, as well as surfaces of the substrate between adjacent memory transistors and selecting transistors; a dielectric layer covering top surfaces of the memory transistors and selecting transistors and fills gaps between each selecting transistor and a corresponding adjacent memory transistor; and air gaps formed between adjacent memory transistors. Each selecting transistor is used for selecting one column of memory transistors in the memory transistor array. The functional layer has a roughened surface capable of absorbing water. The air gaps in the flash memory are water vapor induced air gaps.

Disclosed are systems and methods for improving front-side process uniformity by back-side doping. In some implementations, a highly conductive doped layer can be formed on the back side of a semiconductor wafer prior to certain process steps such as plasma-based processes. Presence of such a back-side doped layer reduces variations in, for example, thickness of a deposited and/or etched layer resulting from the plasma-based processes. Such reduction in thickness variations can result from reduced variation in radio-frequency (RF) coupling during the plasma-based processes.

There is provided a technique that includes: (a) forming an oxide layer containing a predetermined element on a first film formed on a substrate by supplying a precursor gas containing the predetermined element to the substrate such that hydroxyl group terminations are formed on a surface of the oxide layer and a density of the hydroxyl group terminations on the oxide layer is higher than a density of hydroxyl group terminations on a surface of the first film before (a); and (b) hydrophobizing the surface of the oxide layer by supplying a modifying gas containing a hydrocarbon group to the substrate.

A method for making a high-voltage thick gate oxide, which includes depositing a pad silicon oxide on a silicon substrate and depositing a pad silicon nitride on the pad silicon oxide; performing shallow trench isolation photolithography, etching, silicon oxide filling and chemical mechanical polishing; sequentially depositing a mask silicon nitride and a mask silicon oxide on a silicon wafer; removing the mask silicon oxide and the mask silicon nitride in a high-voltage thick gate oxide region, and remaining the pad silicon nitride between two shallow trench isolations in the high-voltage thick gate oxide region; performing first thermal oxidation growth; removing the pad silicon nitride between the two shallow trench isolations in the high-voltage thick gate oxide region; performing second thermal oxidation growth to produce a high-voltage thick gate oxide.

Techniques herein include methods for selectively modifying chemical properties of organosilicates including periodic mesoporous organosilicates (PMOs) in situ for use in fabrication of semiconductor devices. With techniques herein, such materials are manipulated in their chemical properties after deposition and can accordingly be used as sacrificial patterning films and/or as patterning enabling materials. Using selective treatments such as annealing, curing, plasma exposure, and silylation, chemical properties such as etch resistance and hydrophobicity can be changed to enable a given patterning operation. A given film can be etch resistant for one patterning operation, and then changed to be etch removable for a subsequent patterning operation.

In some embodiments, a flash memory and a fabricating method thereof are provided. The method includes proving a substrate including multiple memory transistors and selecting transistors; forming a functional layer covering outer surfaces of the memory transistors and selecting transistors, and surfaces of the substrate between adjacent memory transistors and selecting transistors; performing a surface roughening treatment to the functional layer to provide a roughed surface of the functional layer that absorbs water; and forming a dielectric layer using a chemical vapor deposition (CVD) process, the absorbed water is evaporated from the functional layer during the CVD process to form an upward air flow that resists the deposition of the dielectric layer, such that air gaps are formed between adjacent memory transistors, and the dielectric layer covers top surfaces of the plurality of memory transistors and selecting transistors and fills gaps between each selecting transistor and corresponding adjacent memory transistor.

There is provided a surface treatment method of a glass substrate having a pit on a surface thereof, a production method of an array substrate comprising this method, and an array substrate. The method includes: forming a layer of SiO.sub.2 sol at least at a side wall of the pit; and drying the layer of SiO.sub.2 sol to form a smoothening layer so as to smoothen an upper edge and a lower edge of the side wall of the pit.

A method of manufacturing a memory device including following steps is provided. A first dielectric layer and a first conductive layer are formed in order on the substrate. A first opening and a second opening on the first opening are formed in the substrate, the first dielectric layer and the first conductive layer. An isolation structure is formed in the first opening. A second dielectric layer is formed on the substrate to conformally cover a top surface of the first conductive layer and a surface of the second opening. A heat treatment is performed on the second dielectric layer to enhance the bonding between the second dielectric layer and the first conductive layer. An etching process is performed, so as to remove a portion of the second dielectric layer and expose a top surface of the isolation structure.

A method for etching a metal oxide layer on a semiconductor substrate, comprising providing a plurality of cycles, is provided. Each cycle comprises exposing the metal oxide layer to a reactive hydrogen-containing gas or plasma to transform a part of the metal oxide layer into a layer of metal hydride, stopping the exposing the metal oxide layer to the reactive hydrogen-containing gas or plasma, heating the layer of metal hydride to at least a sublimation temperature to sublime the layer of metal hydride, and cooling the metal oxide layer to a temperature below the sublimation temperature.