In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.

Examples of an integrated circuit with a gate structure and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate having a channel region. A gate dielectric is formed on the channel region, and a layer containing a dopant is formed on the gate dielectric. The workpiece is annealed to transfer the dopant to the gate dielectric, and the layer is removed after the annealing. In some such examples, after the layer is removed, a work function layer is formed on the gate dielectric and a fill material is formed on the work function layer to form a gate structure.

The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a substrate; forming a source and a drain that are at least partially located in the substrate; forming a diffused layer on a surface of at least one of the source or the drain, where a conductivity type of the diffused layer is the same conductivity type as the source and the drain, and a doping density of a dopant contained in the diffused layer is separately greater than doping densities of dopants contained in the source and the drain; and performing an annealing processing after the diffused layer is formed. The present disclosure can increase a doping density at a surface of a source and/or a drain, helping to reduce a contact resistance, thereby improving performance of a device.

One illustrative method disclosed includes, among other things, forming a first dielectric layer and forming first and second conductive structures comprising cobalt embedded in the first dielectric layer. A second dielectric layer is formed above and contacting the first dielectric layer. The first and second dielectric layers comprise different materials, and a portion of the second dielectric layer comprises carbon or nitrogen. A first cap layer is formed above the first and second conductive structures and the second dielectric layer.

According to a mode of the present invention, a method of manufacturing an electronic component includes: preparing a component main-body 110 including a first surface having an electrode-formed region having a plurality of bump electrodes 103, a second surface opposite to the first surface, and side peripheral surfaces connecting the first surface and the second surface; forming a mask section M1 on at least a peripheral portion of the first surface, the mask section surrounding the electrode-formed region, a height of the mask section being equal to or more than a height of the plurality of bump electrodes; bonding the mask section of the first surface to an adhesive layer 30 on a holder for holding a component; forming a protective film 105 on the component main-body, the protective film covering the second surface and the side peripheral surfaces; and removing the mask section M1 from the first surface.

The present disclosure provides a technique including a method of manufacturing a semiconductor device, which is capable of improving the characteristics of a film formed on a substrate. The method of manufacturing a semiconductor device may include: (a) forming a first film containing a predetermined element, oxygen, carbon and nitrogen on a substrate; and (b) forming a second film thinner than the first film on a top surface of the first film, the second film having an oxygen concentration lower than an oxygen concentration of the first film or having oxygen and carbon concentrations lower than oxygen and carbon concentrations of the first film.

A transistor device disclosed herein includes, among other things, a gate electrode positioned above a semiconductor material region, a sidewall spacer positioned adjacent the gate electrode, a gate insulation layer having a first portion positioned between the gate electrode and the semiconductor material region and a second portion positioned between a lower portion of the sidewall spacer and the gate electrode along a portion of a sidewall of the gate electrode, an air gap cavity located between the sidewall spacer and the gate electrode and above the second portion of the gate insulation layer, and a gate cap layer positioned above the gate electrode, wherein the gate cap layer seals an upper end of the air gap cavity so as to define an air gap positioned adjacent the gate electrode.

A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.

The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a substrate; forming a source and a drain that are at least partially located in the substrate; forming a diffused layer on a surface of at least one of the source or the drain, where a conductivity type of the diffused layer is the same conductivity type as the source and the drain, and a doping density of a dopant contained in the diffused layer is separately greater than doping densities of dopants contained in the source and the drain; and performing an annealing processing after the diffused layer is formed. The present disclosure can increase a doping density at a surface of a source and/or a drain, helping to reduce a contact resistance, thereby improving performance of a device.

Fin-like field effect transistors (FinFETs) having high mobility strained channels and methods of fabrication thereof are disclosed herein. An exemplary method includes forming a first silicon fin in a first type FinFET device region and a second silicon fin in a second type FinFET device region. First epitaxial source/drain features and second epitaxial source/drain features are formed respectively over first source/drain regions of the first silicon fin second source/drain regions of the second silicon fin. A gate replacement process is performed to form a gate structure over a first channel region of the first silicon fin and a second channel region of the second silicon fin. During the gate replacement process, a masking layer covers the second channel region of the second silicon fin when a silicon germanium channel capping layer is formed over the first channel region of the first silicon fin.