A method for forming a semiconductor memory structure includes forming a hard mask layer over a semiconductor substrate, etching the hard mask layer to form first mask patterns and second mask patterns, transferring the first and second mask patterns to the substrate to form semiconductor blocks, and thinning down the second mask element. After thinning down the second mask element, the thickness of the second mask elements is less than the thickness of the first mask elements. The method also includes forming a first capping layer to laterally extend over the first mask patterns and the second mask patterns, and etching the first capping layer and the second mask pattern to form contact openings.

A semiconductor structure includes a substrate; a nucleation layer located above the substrate; and a metal nitride thin film located between the nucleation layer and the substrate. A diffusion of atoms in a material of the substrate is suppressed by depositing the metal nitride thin film between the substrate and the nucleation layer, so that a thickness of the nucleation layer is significantly reduced, and a total thermal resistance of the semiconductor structure is reduced.

The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.

The present disclosure provides a thin film transistor, a method for preparing the same, a display substrate, and a display device. The thin film transistor includes a gate electrode, a semiconductor layer, and a gate insulation layer arranged between the gate electrode and the semiconductor layer, and the gate insulation layer includes a metal oxide layer and a modified layer formed through self-assembling on a side of the metal oxide layer away from the gate electrode and.

A method includes forming a silicon layer on a wafer, forming an oxide layer in contact with the silicon layer, and, after the oxide layer is formed, annealing the wafer in an environment comprising ammonia (NH.sub.3) to form a dielectric barrier layer between, and in contact with, the silicon layer and the oxide layer. The dielectric barrier layer comprises silicon and nitrogen.

An integrated circuit includes: a front end of line (FEOL) circuit including a transistor; and a back end of line circuit above the FEOL circuit and including insulator material having an interconnect feature therein. The interconnect feature includes: a core including copper; a first layer between the insulator material and the core, the first layer being distinct from the core; a second layer between the first layer and the core, the second layer being distinct from the first layer and the core, the second layer including a first metal and a second metal different from the first metal; and a capping member on the core and the second layer, the capping member including the second metal. In an embodiment, the first metal and the second metal are part of a solid solution in the second layer. In an embodiment, the first metal is ruthenium and the second metal is cobalt.

Methods of conformally doping three dimensional structures are discussed. Some embodiments utilize conformal silicon films deposited on the structures. The silicon films are doped after deposition to comprise halogen atoms. The structures are then annealed to dope the structures with halogen atoms from the doped silicon films.

The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

A semiconductor device includes a fin structure protruding from a first isolation insulating layer provided over a substrate, a gate dielectric layer disposed over a channel region of the fin structure, a gate electrode layer disposed over the gate dielectric layer, a base semiconductor epitaxial layer disposed over a source/drain region of the fin structure, and a cap semiconductor epitaxial layer disposed over the base semiconductor epitaxial layer. The cap semiconductor epitaxial layer has a different lattice constant than the base semiconductor epitaxial layer, and a surface roughness of the cap semiconductor epitaxial layer along a source-to-drain direction is greater than zero and smaller than a surface roughness of the base semiconductor epitaxial layer along the source-to-drain direction.

Recesses may be formed in portions of an ILD layer of a semiconductor device in a highly uniform manner. Uniformity in depths of the recesses may be increased by configuring flows of gases in an etch tool to promote uniformity of etch rates (and thus, etch depth) across the semiconductor device, from semiconductor device to semiconductor device, and/or from wafer to wafer. In particular, the flow rates of gases at various inlets of the etch tool may be optimized to provide recess depth tuning, which increases the process window for forming the recesses in the portions of the ILD layer. In this way, the increased uniformity of the recesses in the portions of the ILD layer enables highly uniform capping layers to be formed in the recesses.