In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.

A method for fabricating a semiconductor device including a self-aligned top via includes subtractively etching a conductive layer to form at least a first conductive line on a substrate. After the subtractive etching, the method further includes forming a barrier layer along the substate and along the first conductive line, planarizing at least portions of the barrier layer to obtain at least an exposed first conductive line, recessing at least the exposed first conductive line to form a first recessed conductive line, and forming conductive material in a via opening on the first recessed conductive line.

A method of forming a pattern in a photoresist layer includes forming a photoresist layer over a substrate, and reducing moisture or oxygen absorption characteristics of the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.

Examples of an integrated circuit with a gate structure and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate having a channel region. A gate dielectric is formed on the channel region, and a layer containing a dopant is formed on the gate dielectric. The workpiece is annealed to transfer the dopant to the gate dielectric, and the layer is removed after the annealing. In some such examples, after the layer is removed, a work function layer is formed on the gate dielectric and a fill material is formed on the work function layer to form a gate structure.

Methods of conformally doping three dimensional structures are discussed. Some embodiments utilize conformal silicon films deposited on the structures. The silicon films are doped after deposition to comprise halogen atoms. The structures are then annealed to dope the structures with halogen atoms from the doped silicon films.

A semiconductor device structure is provided. The semiconductor device structure includes a conductive gate stack formed over a substrate. A gate dielectric layer covers opposite sidewalls and a bottom of the conductive gate stack. A first gate spacer layer and a second gate spacer layer respectively cover portions of the gate dielectric layer corresponding to the opposite sidewalls of the conductive gate stack. A source/drain contact structure is separated from the conductive gate stack by the gate dielectric layer and the first gate spacer layer. A first insulating capping feature covers the conductive gate stack and is separated from the second gate spacer layer by the gate dielectric layer, and a second insulating capping feature covers the source/drain contact structure. An upper surface of the second insulating capping feature is substantially level with an upper surface of the first insulating capping feature.

An electronic device includes: a water impermeable substrate; at least one electronic circuit on the water impermeable substrate; a dielectric encapsulant on the electronic circuit; a capping layer comprising a polymer on the dielectric encapsulant; and a barrier layer on the capping layer, the water impermeable substrate, the dielectric encapsulant, the capping layer, and the barrier layer forming a hermetically sealed micro-cavity.

A method for forming a semiconductor memory structure includes forming a hard mask layer over a semiconductor substrate, etching the hard mask layer to form first mask patterns and second mask patterns, transferring the first and second mask patterns to the substrate to form semiconductor blocks, and thinning down the second mask element. After thinning down the second mask element, the thickness of the second mask elements is less than the thickness of the first mask elements. The method also includes forming a first capping layer to laterally extend over the first mask patterns and the second mask patterns, and etching the first capping layer and the second mask pattern to form contact openings.

Interconnect structures and methods for forming the interconnect structures generally include forming a bulk metal encapsulated in first and second interlayer dielectrics, a liner layer about a lower surface of the bulk metal and a metal cap layer about an upper surface of the bulk metal. The liner layer is in the first interlayer dielectric and the metal cap layer is in the second interlayer dielectric, wherein liner layer and the metal cap layer are different metals.

The present invention relates to new aromatic-amino functional siloxanes, which are compounds comprising one or two tail groups X.sub.2, and a linking group L of structure (2) linking each said tail group to said head group, wherein the head group X has structure (1), containing an optional organic moiety Y, wherein the attachment point of said tail group X.sub.2 through said linking group L to the head group X.sub.1, may be, at positions a, b, c, d, or e. Another aspect of this invention are compositions containing these novel aromatic amino functional siloxane. A further aspect of this invention are compositions comprised of the above novel aromatic-amino functional siloxanes, and also the composition resulting from the aging of these compositions at room temperature for about 1 day to about 4 weeks. Still further aspects of this invention are processes for forming self-assembled monolayers on a substrate, from the aged composition, and also the processes of coating these aged compositions on patterned porous dielectrics to cap them also the processes of metallization of these capped pattered porous dielectrics. ##STR00001##