A reverse blocking IGBT is manufactured using a silicon wafer sliced from a single crystal silicon ingot which is manufactured by a floating method using a single crystal silicon ingot manufactured by a Czochralski method as a raw material. A separation layer for ensuring a reverse blocking performance of the reverse blocking IGBT is formed by diffusing impurities implanted into the silicon wafer using a thermal diffusion process. The thermal diffusion process for forming the separation layer is performed in an inert gas atmosphere at a temperature equal to or more than 1290 C. and less than the melting point of silicon. In this way, no crystal defect occurs in the silicon wafer and it is possible to prevent the occurrence of a reverse breakdown voltage defect or a forward defect in the reverse blocking IGBT and thus improve the yield of a semiconductor element.

Methods and structures for reducing process and final deformation of gallium nitride (GaN) semiconductor devices are provided. The methods include forming at least one multi-layered structure on at least one surface(s) a semiconductor substrate. The multi-layered structure(s) are formed by applying at least a first amorphous layer on at least one surface(s) of the semiconductor substrate, the first amorphous layer having a first thermal expansion coefficients (CTE), and applying a second amorphous layer on the first amorphous layer, the second amorphous layer having a second thermal expansion coefficient, different from the first thermal expansion coefficient.

Techniques are disclosed for using a high resistance layer between a III-V channel layer and a group IV substrate for semiconducting devices, such as metal-oxide-semiconductor (MOS) transistors. The high resistance layer can be used to minimize (or eliminate) current flow from source to drain that follows a path other than directly through the channel. In some cases, the high resistance layer may be a III-V wide bandgap layer. In some such cases, the wide bandgap layer may have a bandgap greater than 1.4 electron volts (eV), and may even have a bandgap greater than 2.0 eV. In other cases, the wide bandgap layer may be partially or completely converted to an insulator through oxidation or nitridation, for example. The resulting structures may be used with planar, finned, or nanowire/nanoribbon transistor architectures to help prevent substrate leakage problems.

Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

Graphite-based devices with a reduced characteristic dimension and methods for forming such devices are provided. One or more thin films are deposited onto a substrate and undesired portions of the deposited thin film or thin films are removed to produce processed elements with reduced characteristic dimensions. Graphene layers are generated on selected processed elements or exposed portions of the substrate after removal of the processed elements. Multiple sets of graphene layers can be generated, each with a different physical characteristic, thereby producing a graphite-based device with multiple functionalities in the same device.

According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

The invention relates to a method for fabricating a semiconductor circuit comprising providing a semiconductor substrate; fabricating a first semiconductor device comprising a first semiconductor material on the substrate and forming an insulating layer comprising a cavity structure on the first semiconductor device. The cavity structure comprises at least one growth channel and the growth channel connects a crystalline seed surface of the first semiconductor device with an opening. Further steps include growing via the opening from the seed surface a semiconductor filling structure comprising a second semiconductor material different from the first semiconductor material in the growth channel; forming a semiconductor starting structure for a second semiconductor device from the filling structure; and fabricating a second semiconductor device comprising the starting structure. The invention is notably also directed to corresponding semiconductor circuits.

In various embodiments, a method of forming a graphene structure is provided. The method may include forming a body including at least one protrusion, and forming a graphene layer at an outer peripheral surface of the at least one protrusion.

According to an embodiment of a method of fabricating III-Nitride semiconductor dies, the method includes: growing a III-Nitride body over a group IV substrate in a semiconductor wafer; forming at least one device layer over the III-Nitride body; etching grid array trenches in the III-Nitride body and in the group IV substrate; forming an edge trench around a perimeter of the semiconductor wafer, the grid array trenches terminating inside the group IV substrate; and forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.

In various embodiments, a method of forming a graphene structure is provided. The method may include forming a body including at least one protrusion, and forming a graphene layer at an outer peripheral surface of the at least one protrusion.