High germanium percentage (40 atomic percent or greater) silicon germanium (SiGe) graded buffer layers are provided in which stacking fault formation and dislocation defect density are drastically suppressed. Notably, a lattice matched heterogeneous semiconductor material interlayer of Ga(As.sub.1-yP.sub.y) wherein y is from 0 to 1 is formed between each of the SiGe layers of the graded buffer layer to reduce the propagation of threading arm dislocation to the surface and inhibit the formation of stacking faults in each subsequent SiGe layer, and therewith drastically reduce the surface defect density.

High germanium percentage (40 atomic percent or greater) silicon germanium (SiGe) graded buffer layers are provided in which stacking fault formation and dislocation defect density are drastically suppressed. Notably, a lattice matched heterogeneous semiconductor material interlayer of Ga(As.sub.1-yP.sub.y) wherein y is from 0 to 1 is formed between each of the SiGe layers of the graded buffer layer to reduce the propagation of threading arm dislocation to the surface and inhibit the formation of stacking faults in each subsequent SiGe layer, and therewith drastically reduce the surface defect density.

A semiconductor stacked body includes: a first semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a first conductivity type; a quantum-well light-receiving layer containing a group III-V compound semiconductor; a second semiconductor layer containing a group III-V compound semiconductor; and a third semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a second conductivity type. The first semiconductor layer, the quantum-well light-receiving layer, the second semiconductor layer, and the third semiconductor layer are stacked in this order. The concentration of an impurity that generates a carrier of the second conductivity type is 110.sup.14 cm.sup.3 or more and 110.sup.17 cm.sup.3 or less in the second semiconductor layer.

A method for printing a semiconductor material includes depositing a molten metal onto a substrate in an enclosed chamber to form a trace having a maximum height of 15 micrometers, a maximum width of 25 micrometers to 10 millimeters, and/or a thin film having a maximum height of 15 micrometers. The method further includes reacting the molten metal with a gas phase species in the enclosed chamber to form the semiconductor material.

A method for fabricating a semiconductor substrate comprises providing a crystalline base substrate, forming an insulating layer on the crystalline base substrate and forming a trench in the insulating layer. This exposes a seed surface of the base substrate. The trench has sidewalls and a bottom. The bottom corresponds to the seed surface of the base substrate. The method further comprises growing, at a first growth step, an elongated seed structure in the trench from the seed surface of the substrate and forming a cavity structure above the insulating layer. The cavity structure covers the elongated seed structure and extends laterally to the elongated seed structure. The method comprises a further step of growing, at a second growth step, the semiconductor substrate in the cavity structure from the elongated seed structure. The invention is notably also directed to corresponding semiconductor structures and corresponding semiconductor substrates.

A transition metal dichalcogenide (TMD) transistor includes a substrate, an n-type two-dimensional (2D) TMD layer, a metal source electrode, a metal drain electrode, and a gate dielectric. The substrate has a top portion that is an insulating layer, and the n-type 2D TMD layer is on the insulating layer. The metal source electrode, the metal drain electrode, and the gate dielectric are on the n-type 2D TMD layer. The metal gate electrode is on top of the gate dielectric and is between the metal source electrode and the metal drain electrode.

The invention relates to an optoelectronic device (1) comprising at least one three-dimensional semiconductor structure (2) extending along a longitudinal axis () substantially orthogonal to a plane of a substrate (3) on which same lies, and comprising: a first doped portion (10), extending from one surface of the substrate (3) along the longitudinal axis (); an active portion (30) comprising a passivation layer (34) and at least one quantum well (32) covered laterally by said passivation layer (34), the quantum well (32) of the active portion (30) having a mean diameter greater than that of said first doped portion (10), said active portion (30) extending from the first doped portion (10) along the longitudinal axis (); and a second doped portion (20), extending from the active portion (30) along the longitudinal axis (). The invention is characterized in that the device comprises a plurality of three-dimensional semiconductor structures (2) extending substantially in parallel with one another, the active portions (30) of which are in mutual contact.

Methods for depositing silicon include cycling dosing between 1 and 100 cycles of one or more first chlorosilane precursors on a III-V surface at a temperature between 300 C. and 500 C. to form a first layer. Methods may include desorbing chlorine from the first layer by treating the first layer with atomic hydrogen to form a second layer. Methods may include forming a silicon multilayer on the second layer by cycling dosing between 1 and 100 cycles of one or more second chlorosilane precursors and atomic hydrogen at a temperature between 300 C. and 500 C. A layered composition includes a first layer selected from the group consisting of In.sub.xGa.sub.1xAs, In.sub.xGa.sub.1xSb, In.sub.xGa.sub.1xN, SiGe, and Ge, wherein X is between 0.1 and 0.99, and a second layer, wherein the second layer comprises SiH and SiOH.

A multilayer device includes a substrate and a first layer disposed on the substrate. A trench extends through one or both of the substrate and the first layer. The trench has a first sidewall spaced apart from a second sidewall, each sidewall extending from an upper surface of the substrate to a lower surface of the first layer. An optically active region is disposed on the first layer overlying the trench, such that at least a portion of the optically active region is located within a set of lines corresponding to the sidewalls of the trench.

A method for formation of a transition metal dichalcogenide (TMDC) material layer on a substrate arranged in a process chamber of a molecular beam epitaxy tool is provided. The method includes evaporating metal from a solid metal source, forming a chalcogen-including gas-plasma, and introducing the evaporated metal and the chalcogen-including gas-plasma into the process chamber thereby forming a TMDC material layer on the substrate.