A multilayer device includes a substrate and a first layer disposed on the substrate. A trench extends through one or both of the substrate and the first layer. The trench has a first sidewall spaced apart from a second sidewall, each sidewall extending from an upper surface of the substrate to a lower surface of the first layer. An optically active region is disposed on the first layer overlying the trench, such that at least a portion of the optically active region is located within a set of lines corresponding to the sidewalls of the trench.

A method of producing a pre-patterned structure comprising at least one cavity for growing a vertical nanostructure is disclosed. The method includes providing at least one protruding structure that extends upwardly from a main surface of a substrate. The at least one protruding structure has a main portion of a first height and an upper portion on the main portion. The method also includes embedding the at least one protruding structure in a dielectric material. Further, the method includes removing at least an excess portion of the dielectric material, thereby exposing a top surface of the upper portion and forming a flattened surface of the top surface of the upper portion and the dielectric material. In addition, the method includes forming at least one cavity of a first depth by removing the upper portion, thereby exposing a top surface of the main portion of the at least one protruding structure.

Method for fabricating a semiconductor structure. The method includes: providing a crystalline silicon substrate; defining an opening in a dielectric layer on the crystalline silicon substrate, the opening having sidewalls and a bottom wherein the bottom corresponds to a surface of the crystalline silicon substrate; providing a confinement structure above the dielectric layer, thereby forming a confinement region between the confinement structure and the dielectric layer; and growing a crystalline compound semiconductor material in the confinement region thereby at least partially filling the confinement region. The present invention also provides an improved compound semiconductor structure and a device for fabricating such semiconductor structure.

Methods for depositing silicon on a semiconductor or metallic surface include cycling dosing of silane and chlorosilane precursors at a temperature between 50 C. and 300 C., and continuing cycling between three and twenty three cycles until the deposition self-limits via termination of surface sites with SiH groups. Methods of layer formation include depositing a chlorosilane onto a substrate to form a first layer, wherein the substrate is selected from the group consisting of In.sub.xGa.sub.1-xAs, In.sub.xGa.sub.1-xSb, In.sub.xGa.sub.1-xN, SiGe, and Ge, wherein X is between 0.1 and 0.99. The methods may include pulsing a silane to form a silicon monolayer and cycling dosing of the chlorosilane and the silane. Layered compositions include a first layer selected from the group consisting of In.sub.xGa.sub.1-xAs, In.sub.xGa.sub.1-xSb, In.sub.xGa.sub.1-xN, SiGe, and Ge, wherein X is between 0.1 and 0.99, and a second layer, wherein the second layer comprises SiH and SiOH.

A method includes placing at least two substrates on a substrate carrier at a distance from one another, placing the substrate carrier in a reaction chamber, depositing a precursor on the at least two substrates, and performing a first annealing process on the at least two substrates. The at least two substrates include a first content of a first material. The distance between the at least two substrates is based on the first content of the first material and at least one processing parameter. The disclosed method advantageously provides for improved Na-dosing control.

A process of depositing germanium on a substrate includes sequentially exposing in at least one deposition cycle the substrate inside a chamber with a Ge-containing precursor and a reducing or oxidizing precursor.

Method for fabricating a semiconductor structure. The semiconductor structure includes: a crystalline silicon substrate; a dielectric layer on the crystalline silicon substrate, the opening having an opening with sidewalls and a bottom wherein the bottom corresponds to a surface of the crystalline silicon substrate; and a crystalline compound semiconductor layer thereby forming a processable crystalline compound semiconductor substrate, wherein the bottom of the opening is isolated from the crystalline compound material.

A seed layer for inducing nucleation to form a layer of material is described. In an embodiment, the seed layer comprising a layer of two-dimensional monolayer amorphous material having a disordered atomic structure adapted to create localised electronic states to form electric potential wells for bonding adatoms to a surface of the seed layer via van der Waals interaction to form the layer of material, wherein each of the electric potential wells has a potential energy larger in magnitude than surrounding thermal energy to capture adatoms on the surface of the seed layer. Embodiments in relation to a method for forming the seed layer, a heterostructure comprising the seed layer, a method for forming the heterostructure comprising the seed layer, a device comprising the heterostructure and a method of enhancing vdW interaction between adatoms and a surface of the seed layer are also described.

A method for flattening a surface on an epitaxial lateral overgrowth (ELO) layer, resulting in obtaining a smooth surface with island-like III-nitride semiconductor layers. The island-like III-nitride semiconductor layers are formed by stopping the growth of the ELO layers before they coalesce to each other. Then, a growth restrict mask is removed before at least some III-nitride device layers are grown. Removing the mask decreases an excess gases supply to side facets of the island-like III-nitride semiconductor layers, which can help to obtain a smooth surface on the island-like III-nitride semiconductor layers. The method also avoids compensation of a p-type layer by decomposed n-type dopant from the mask, such as Silicon and Oxygen atoms.