A transition metal dichalcogenide transistor, comprising: a gate, a gate dielectric layer and a channel layer from bottom to top, a source/drain region are located on both the sides of the gate dielectric layer, wherein, in a plane paralleled to the channel layer, the length of the channel layer in each direction is greater than the length of the gate dielectric layer, and the length of the gate dielectric layer in each direction is greater than or equal to the length of the gate; wherein, the source/drain region are a first transition metal dichalcogenide with metallic properties, and the channel layer is a second transition metal dichalcogenide with semiconductor properties. The present invention provides a transition metal dichalcogenide transistor and a preparation method thereof, which can solve a problem of excessive contact resistance between a transition metal dichalcogenide transistor channel and a source/drain region and can make the transition metal dichalcogenide transistor compatible with the existing CMOS process.

Disclosed is a method for synthesizing single crystalline molybdenum disulfide via a hydrothermal process that minimizes or eliminates carbon byproducts. The method involves providing two components, including a source of molybdenum and a mineralizer solution, to an inert reaction vessel, heating one zone sufficiently to dissolve the source of molybdenum in the mineralizer solution, and heating a second zone to a lower temperature to allow thermal transport to drive the dissolved material to the second zone, and then precipitate MoS.sub.2 on a seed crystal.

According to various embodiments, there is provided a diode device including a semiconductor substrate of a first conductivity type, a first semiconductor region formed within the semiconductor substrate, an epitaxial region of the first conductivity type, and a second semiconductor region of a second conductivity type different from the first conductivity type. The first semiconductor region includes a chalcogen. The epitaxial region is formed over the first semiconductor region. The second semiconductor region is formed over the epitaxial region.

A transition metal dichalcogenide transistor, comprising: a gate, a gate dielectric layer and a channel layer from bottom to top, a source/drain region are located on both the sides of the gate dielectric layer, wherein, in a plane paralleled to the channel layer, the length of the channel layer in each direction is greater than the length of the gate dielectric layer, and the length of the gate dielectric layer in each direction is greater than or equal to the length of the gate; wherein, the source/drain region are a first transition metal dichalcogenide with metallic properties, and the channel layer is a second transition metal dichalcogenide with semiconductor properties. The present invention provides a transition metal dichalcogenide transistor and a preparation method thereof, which can solve a problem of excessive contact resistance between a transition metal dichalcogenide transistor channel and a source/drain region and can make the transition metal dichalcogenide transistor compatible with the existing CMOS process.

Provided are two-dimensional material (2D)-based wiring conductive layer contact structures, electronic devices including the same, and methods of manufacturing the electronic devices. A 2D material-based field effect transistor includes a substrate; first to third 2D material layers on the substrate; an insulating layer on the first 2D material layer; a source electrode on the second 2D material layer; a drain electrode on the third 2D material layer; and a gate electrode on the insulating layer. The first 2D material layer is configured to exhibit semiconductor characteristics, and the second and third 2D material layers are metallic 2D material layers. The first 2D material layer may include a first channel layer of a 2D material and a second channel layer of a 2D material. The first 2D material layer may partially overlap the second and third 2D material layers.

A PCSS comprises a photoconductive semiconductor block that exhibits electrically-conductive behavior when exposed to light of a predetermined wavelength; two or more electrodes fixed to the photoconductive semiconductor block and connectable to a power supply; a resonance cavity enveloping the photoconductive semiconductor block, the resonance cavity having a reflective outer surface to trap light within the resonance cavity and the photoconductive semiconductor block, the resonance cavity having a window through the reflective outer surface to admit light of the predetermined wavelength, the resonance cavity being transmissive to light of the predetermined wavelength within the reflective outer surface; and a light source directed toward the photoconductive semiconductor block and through the window, and emitting light at the predetermined wavelength. The photoconductive semiconductor block may include Si, GaAs, GaN, AlN, SiC, and/or Ga.sub.2O.sub.3. The resonance cavity may include glass, crystal, Au, Ag, Cr, Ni, V, Pd, Pt, Ir, Rh, and/or Al.

A PCSS comprises a photoconductive semiconductor block that exhibits electrically-conductive behavior when exposed to light of a predetermined wavelength; two or more electrodes fixed to the photoconductive semiconductor block and connectable to a power supply; a resonance cavity enveloping the photoconductive semiconductor block, the resonance cavity having a reflective outer surface to trap light within the resonance cavity and the photoconductive semiconductor block, the resonance cavity having a window through the reflective outer surface to admit light of the predetermined wavelength, the resonance cavity being transmissive to light of the predetermined wavelength within the reflective outer surface; and a light source directed toward the photoconductive semiconductor block and through the window, and emitting light at the predetermined wavelength. The photoconductive semiconductor block may include Si, GaAs, GaN, AlN, SiC, and/or Ga.sub.2O.sub.3. The resonance cavity may include glass, crystal, Au, Ag, Cr, Ni, V, Pd, Pt, Ir, Rh, and/or Al.

There is a method for forming a semiconductor nanostructure on a substrate. The method includes placing a substrate and a semiconductor material in a pulsed laser deposition chamber; selecting parameters including a fluence of a laser beam, a pressure P inside the chamber, a temperature T of the substrate, a distance d between the semiconductor material and the substrate, and a gas molecule diameter a.sub.0 of a gas to be placed inside the chamber so that conditions for a Stranski-Krastanov nucleation are created; and applying the laser beam with the selected fluence to the semiconductor material to form a plume of the semiconductor material. The selected parameters determine the formation, from the plume, of (1) a nanolayer that covers the substrate, (2) a polycrystalline wetting layer over the nanolayer, and (3) a single-crystal nanofeature over the polycrystalline wetting layer, and the single-crystal nanofeature is grown free of any catalyst or seeding layer.

Disclosed herein are methods for exfoliation of single crystals allowing for growth of high crystalline quality on the exfoliated surfaces for III-V photovoltaics. Also disclosed herein are methods for growing GaAs (111) on layered-2D Bi.sub.2Se.sub.3 (0001) substrates in an MOCVD reactor.

A method for fabricating an electronic device including a semiconductor memory includes forming a chalcogenide layer, forming a first conductive layer on the chalcogenide layer, and increasing a density of an interface between the chalcogenide layer and the first conductive layer by injecting or irradiating ions onto the interface.