High electron mobility transistors are provided which comprise a III-Nitride semiconductor layer comprising a III-Nitride semiconductor, in contact with a gallium oxide semiconductor layer comprising gallium oxide, forming an interface therebetween.

A multilayer diamond system includes an optically transparent substrate and an optically transparent intermediate layer deposited on the optically transparent substrate. A diamond layer is deposited on the optically transparent intermediate layer and formed from diamond having at least 50% of diamond grains sized between 2 nm and 500 nanometers.

The present invention includes: transferring a C-plane sapphire thin film 1t having an off-angle of 0.5-5° onto a handle substrate composed of a ceramic material having a coefficient of thermal expansion at 800 K that is greater than that of silicon and less than that of C-plane sapphire; performing high-temperature nitriding treatment on the GaN epitaxial growth substrate 11 and covering the surface of the C-plane sapphire thin film 1t with a surface treatment layer 11a made of AlN; having GaN grow epitaxially on the surface treatment layer 11a; ion-implanting a GaN film 13; pasting and bonding together the GaN film-side surface of the ion-implanted GaN film carrier and a support substrate 12; performing peeling at an ion implantation region 13.sub.ion in the GaN film 13 and transferring a GaN thin film 13a onto the support substrate 12; and obtaining a GaN laminate substrate 10.

A semiconductor stacking structure according to the present invention comprises: a monocrystalline substrate which is disparate from a nitride semiconductor; an inorganic thin film which is formed on a substrate to define a cavity between the inorganic thin film and the substrate, wherein at least a portion of the inorganic thin film is crystallized with a crystal structure that is the same as the substrate; and a nitride semiconductor layer which is grown from a crystallized inorganic thin film above the cavity. The method and apparatus for separating a nitride semiconductor layer according the present invention mechanically separate between the substrate and the nitride semiconductor layer. The mechanical separation can be performed by a method of separation of applying a vertical force to the substrate and the nitride semiconductor layer, a method of separation of applying a horizontal force, a method of separation of applying a force of a relative circular motion, and a combination thereof.

A crystal substrate 1 includes an underlying layer 2 and a thick film 3. The underlying layer 2 is composed of a crystal of a nitride of a group 13 element and includes a first main face 2a and a second main face 2b. The thick film 3 is composed of a crystal of a nitride of a group 13 element and provided over the first main face of the underlying layer. The underlying layer 2 includes a low carrier concentration region 5 and a high carrier concentration region 4 both extending between the first main face 2a and the second main face 2b.

The invention relates to heterostructures including a layer of a two-dimensional material placed on a multiferroic layer. An ordered array of differing polarization domains in the multiferroic layer produces corresponding domains having differing properties in the two-dimensional material. When the multiferroic layer is ferroelectric, the ferroelectric polarization domains in the layer produce local electric fields that penetrate the two-dimensional material. The local electric fields modulate the charge carriers and carrier density on a nanometer length scale, resulting in the formation of lateral p-n or p-i-n junctions, and variations thereof appropriate for device functions. Methods for producing the heterostructures are provided. Devices incorporating the heterostructures are also provided.

The present disclosure relates to a method and device for decreasing generation of surface oxide of aluminum nitride. In a physical vapor deposition process, the aluminum nitride is deposited on a substrate in a deposition chamber to form an aluminum nitride coated substrate. A cooling chamber and a cooling load lock module respectively perform a first stage cooling and a second stage cooling on the aluminum nitride coated substrate in vacuum environments, so as to prevent the aluminum nitride coated substrate with the high temperature from being exposed in an atmosphere environment to generate the surface oxide. The method and device for decreasing the generation of the surface oxide of the aluminum nitride can further eliminate crystal defects caused by that gallium nitride is deposited on the surface oxide of the aluminum nitride in the next process.

The present disclosure describes epitaxial oxide high electron mobility transistors (HEMTs). In some embodiments, a HEMT comprises: a substrate; a template layer on the substrate; a first epitaxial semiconductor layer on the template layer; and a second epitaxial semiconductor layer on the first epitaxial semiconductor layer. The template layer can comprise crystalline metallic Al(111). The first epitaxial semiconductor layer can comprise (Al.sub.xGa.sub.1-x).sub.yO.sub.z, wherein 0≤x≤1, 1≤y≤3, and 2≤z≤4, wherein the (Al.sub.xGa.sub.1-x).sub.yO.sub.z comprises a Pna21 space group, and wherein the (Al.sub.xGa.sub.1-x).sub.yO.sub.z comprises a first conductivity type formed via polarization. The second epitaxial semiconductor layer can comprise a second oxide material.

Provided is a semiconductor device including: a semiconductor layer; a non-conductive layer that is in contact with at least a part of a side surface of the semiconductor layer directly or via another layer; and a Schottky electrode that is disposed on the semiconductor layer and the non-conductive layer, an end portion of the Schottky electrode being located above the non-conductive layer.

A transistor includes a channel layer, a gate stack, and source/drain regions. The channel layer includes a graphene layer and hexagonal boron nitride (hBN) flakes dispersed in the graphene layer. Orientations of the hBN flakes are substantially aligned. The gate stack is over the channel layer. The source/drain regions are aside the gate stack.