Disclosed are an array substrate and a manufacturing method therefor, a display panel and a display apparatus. The array substrate comprises several pixel units located on a base substrate and arranged in an array, with each of the pixel units comprising a thin-film transistor, and the thin-film transistor comprising a polycrystalline silicon active layer, wherein a length extension direction of a channel of the thin-film transistor is parallel to a pre-set direction; and the pre-set direction is a scanning direction of an excimer laser beam used when forming the polycrystalline silicon active layer.

A method for manufacturing a plurality of crystalline semiconductor islands having different lattice parameters includes providing a relaxation substrate comprising a support and a flow layer on the support that includes first and second groups of blocks having different viscosities at a relaxation temperature. The relaxation substrate also comprises a plurality of strained crystalline semiconductor islands on the flow layer, the islands of a first group being located on the first group of blocks and islands of a second group being located on the second group of blocks. The relaxation substrate is then heat treated at a relaxation temperature higher than or equal to the glass transition temperature of at least one block of the flow layer to cause differentiated lateral expansion of the first and second groups of islands such that the first and second groups of relaxed islands then have different lattice parameters.

A low temperature polysilicon layer, a thin film transistor, and a method for manufacturing same are provided. The low temperature polysilicon layer includes a substrate, at least one buffer layer, and a polysilicon layer. The polysilicon layer is disposed on the at least one buffer layer. The polysilicon layer includes a channel region, two low doped regions disposed on two sides of the channel region, and two high doped regions disposed on an outer side of the low doped regions. Thicknesses of an edge of the channel region and at least one portion of the low doped regions are less than a thickness of another position of the polysilicon layer.

[Solving Means] An oxide semiconductor thin film according to an embodiment of the present invention includes: an oxide semiconductor that mainly contains In, Sn, and Ge. An atom ratio of Ge/(In+Sn+Ge) is 0.07 or more and 0.40 or less. As a result, it is possible to achieve transistor characteristics with a mobility of 10 cm.sup.2/Vs or more.

A microelectronic device includes a gated graphene component. The gated graphene component has a graphitic layer containing one or more layers of graphene. The graphitic layer has a channel region, a first contact region adjacent to the channel region and a second contact region adjacent to the channel region. A patterned hexagonal boron nitride (hBN) layer is disposed on the graphitic layer above the channel region. A gate is located over the patterned hBN layer above the channel region. A first connection is disposed on the graphitic layer in the first contact region, and a second connection is disposed on the graphitic layer in the second contact region. The patterned hBN layer does not extend completely under the first connection or under the second connection. A method of forming the gated graphene component in the microelectronic device is disclosed.

A sputtering system may inject hydrogen and a sputtering gas into a chamber of the sputtering system, which may cause at least one layer of a hydrogenated semiconductor material, such as hydrogenated silicon (Si:H), to be sputtered onto a substrate disposed in the chamber until the at least one layer has a thickness that satisfies a threshold. In some implementations, the hydrogen and the sputtering gas may be injected into the chamber of the sputtering system while a temperature in the chamber is in a range from 145 degrees Celsius to 165 degrees Celsius. Accordingly, in some implementations, the sputtered layer of the hydrogenated semiconductor material may have one or more optical properties that satisfy a threshold to enable operation in a 9xx nanometer wavelength regime and at larger wavelengths.

Embodiments of the disclosure relate to a method for fabricating semiconductor-on-insulator (SemOI) electronic components. In the method, a device wafer is bonded to a handling wafer. The device wafer includes a semiconductor device layer and a buried oxide layer. A substrate is adhered to the handling wafer. The substrate is a glass or a ceramic, and bonding occurs at an interface between the semiconductor device layer and the substrate. Material is removed from the device wafer to expose the buried oxide layer. The substrate is debonded from the handling wafer so as to provide an SemOI electronic component including the substrate, the semiconductor device layer, and the buried oxide layer.

Example embodiments relate to a method of manufacturing graphene structures having nanobubbles. The graphene structure includes a graphene layer on a substrate, the graphene layer having a plurality of convex portions and a band gap that is due to the plurality of convex portions. The method includes preparing the graphene layer on the substrate, and forming the plurality of convex portions on the graphene layer by irradiating a noble gas onto the graphene layer.

The present invention relates to processes of making components for electronic and optical devices using laser processing and devices comprising such components. Such process uses a laser to introduce chemical and/or structural changes in substrates and films that are the raw materials from which components for electronic and optical devices are made. Such process yields components that can have one or more electronic and/or optical functionalities that are integrated on the same substrate or film. In addition, such process does not require large-scale clean rooms and is easily configurable. Thus, rapid device prototyping, design change and evolution in the lab and on the production side is realized.

A thin-film transistor according to an embodiment of the present invention includes: a gate electrode; an active layer formed of an oxide containing indium, zinc, and titanium; a gate insulating film formed between the gate electrode and the active layer; and a source electrode and a drain electrode that are electrically connected to the active layer. Atomic proportions of elements relative to the total quantity of indium, zinc, and titanium that constitute the oxide may be not less than 24 at. % and not more than 80 at. % for indium, not less than 16 at. % and not more than 70 at. % for zinc, and not less than 0.1 at. % and not more than 20 at. % for titanium.