A method includes depositing a copper layer over a first substrate, annealing the copper layer, depositing a hexagonal boron nitride (hBN) film on the copper layer, and removing the hBN film from the copper layer. The hBN film may be transferred to a second substrate.

A substrate includes a ceramic core, a first adhesion layer, a barrier layer, and a second adhesion layer. The first adhesion layer encapsulates the ceramic core and includes silicon oxynitride, wherein the atomic number ratio of oxygen to nitrogen in silicon oxynitride of the first adhesion layer has a first ratio. The barrier layer encapsulates the first adhesion layer and includes silicon oxynitride, wherein the atomic number ratio of oxygen to nitrogen in silicon oxynitride of the barrier layer has a second ratio that is different from the first ratio. The second adhesion layer encapsulates the barrier layer and includes silicon oxynitride, wherein the atomic number ratio of oxygen to nitrogen in silicon oxynitride of the second adhesion layer has a third ratio that is different from the second ratio.

An InN nanorod epitaxial wafer grown on an aluminum foil substrate (1) sequentially comprises the aluminum foil substrate (1), an amorphous aluminum oxide layer (2), an AlN layer (3) and an InN nanorod layer, (4) from bottom to top. The wafer can be prepared by pretreating the aluminum foil substrate with an oxidized surface and carrying out an in-situ annealing treatment; then, in a molecular beam epitaxial growth process, forming AlN nucleation sites on the annealed aluminum foil substrate, nucleating on the AlN and growing InN nanorods on the AlN. where the substrate temperature is 400-700 C., the pressure of a reaction chamber is 4.0-10.010.sup.5 Torr and the beam ratio of V/III is 20-40.

A memory structure includes a substrate, a gate electrode, a first isolation layer, a thin metal layer, indium gallium zinc oxide (IGZO) particles, a second isolation layer, an IGZO channel layer, and a source/drain electrode. The gate electrode is located on the substrate. The first isolation layer is located on the gate electrode. The thin metal layer is located on the first isolation layer, and has metal particles. The IGZO particles are located on the metal particles. The second isolation layer is located on the IGZO particles. The IGZO channel layer is located on the second isolation layer. The source/drain electrode is located on the IGZO channel layer.

Provided are a graphene preparation apparatus, including: a chamber having a space for preparation of graphene; a first electrode and a second electrode disposed in the chamber to be separated a predetermined distance from each other, the first electrode and the second electrode supporting a catalytic metal and receiving electric current for preparation of the graphene to heat the catalytic metal using Joule heating; additional heaters disposed at opposite sides of the catalytic metal, respectively, and heating the catalytic metal to compensate for a temperature difference between both end regions and a central region of the catalytic metal heated using Joule heating induced by the first electrode and the second electrode; and a current supply unit supplying electric current to the first electrode and the second electrode.

Methods, systems, devices, and products for performing well logging in a borehole intersecting an earth formation. Apparatus include a carrier conveyable in the borehole; a tool disposed on the carrier. The tool comprises a substrate including a first attachment interface electrically connected to a second attachment interface by a substrate connection element, wherein the first attachment interface comprises a first attachment interface material and the second attachment interface comprises a second attachment interface material different than the first attachment interface material; and at least two terminals, each terminal attached to at least one of the first attachment interface material of the substrate and the second attachment interface material of the substrate by a join.

A method of performing regional heating of a substrate by electromagnetic induction heating. The method may include applying a semiconductor film to the substrate and controllably energizing a coil positioned near the substrate. The energized coil(s) thereby generates a magnetic flux, which induces a current in the substrate and/or the semiconductor film, thereby heating the substrate and/or semiconductor film. The method may also include relative motion between the coil and the substrate to provide translation heating of the semiconductor film. Additionally, a crystal seeding mechanism may be employed to further control the crystallization process.

Methods of direct growth of high quality group III-V and group III-N based materials and semiconductor device structures in the form of nanowires, planar thin film, and nanowires-based devices on metal substrates are presented. The present compound semiconductor all-metal scheme greatly simplifies the fabrication process of high power light emitters overcoming limited thermal and electrical conductivity of nanowires grown on silicon substrates and metal thin film in prior art. In an embodiment the methods include: (i) providing a metal substrate; (ii) forming a transition metal dichalcogenide (TMDC) layer on a surface of the metal substrate; and (iii) growing a semiconductor epilayer on the transition metal dichalcogenide layer using a semiconductor epitaxy growth system. In an embodiment, the semiconductor device structures can be compound semiconductors in contact with a layer of metal dichalcogenide, wherein the layer of metal dichalcogenide is in contact with a metal substrate.

The present disclosure provides a method for manufacturing a flexible device having a pattern of a two-dimensional material formed thereon includes: a step of forming a two-dimensional material layer on a substrate; a step of forming a pattern of the two-dimensional material; a step of coating a flexible substrate solution on the patterned two-dimensional material layer and curing the same; and a step of removing the substrate.

A semiconductor device and method for fabricating same is disclosed. Embodiments are directed to a semiconductor device and fabrication of same which include a flexible substrate and a buffer stack overlying the substrate. The buffer stack comprises at least one epitaxial buffer layer. An epitaxial doped layer comprised predominantly of silicon overlies the at least one epitaxial buffer layer. Mobility of the device is greater than 100 cm.sup.2/Vs and carrier concentration of the epitaxial doped layer is less than 10.sup.16 cm.sup.3.