A method for manufacturing a semiconductor device is provided. The method includes forming at least one epitaxial layer over a substrate; forming a mask over the epitaxial layer; patterning the epitaxial layer into a semiconductor fin; depositing a semiconductor capping layer over the semiconductor fin and the mask, wherein the semiconductor capping layer has a first portion that is amorphous on a sidewall of the mask; performing a thermal treatment such that the first portion of the semiconductor capping layer is converted from amorphous into crystalline; forming an isolation structure around the semiconductor fin; and forming a gate structure over the semiconductor fin.

A semiconductor device has a first substrate made of a first semiconductor material, such as silicon. A sacrificial layer is formed over a first surface of the first substrate. A seed layer is formed over the sacrificial layer. A compliant layer is formed over a second surface of the first substrate opposite the first surface of the first substrate. A first semiconductor layer made of a second semiconductor material, such as silicon carbide, dissimilar from the first semiconductor material is formed over the sacrificial layer. The first substrate and sacrificial layer are removed leaving the first semiconductor layer substantially defect-free. The first semiconductor layer containing the second semiconductor material is formed at a temperature greater than a melting point of the first semiconductor material. A second semiconductor layer is formed over the first semiconductor layer with an electrical component formed in the second semiconductor layer.

A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

A method for forming a laterally-grown group III metal nitride crystal includes providing a substrate, the substrate including one of sapphire, silicon carbide, gallium arsenide, silicon, germanium, a silicon-germanium alloy, MgAl.sub.2O.sub.4 spinel, ZnO, ZrB.sub.2, BP, InP, AlON, ScAlMgO.sub.4, YFeZnO.sub.4, MgO, Fe.sub.2NiO.sub.4, LiGa.sub.5O.sub.8, Na.sub.2MoO.sub.4, Na.sub.2WO.sub.4, In.sub.2CdO.sub.4, lithium aluminate (LiAlO.sub.2), LiGaO.sub.2, Ca.sub.8La.sub.2(PO.sub.4).sub.6O.sub.2, gallium nitride, or aluminum nitride (AlN), forming a pattern on the substrate, the pattern comprising growth centers having a minimum dimension between 1 micrometer and 100 micrometers, and being characterized by at least one pitch dimension between 20 micrometers and 5 millimeters, growing a group III metal nitride from the pattern of growth centers vertically and laterally, and removing the laterally-grown group III metal nitride layer from the substrate. A laterally-grown group III metal nitride layer coalesces, leaving an air gap between the laterally-grown group III metal nitride layer and the substrate or a mask thereupon.

Gate-all-around integrated circuit structures having germanium nanowire channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium nanowire channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, each of the nanowires including germanium, and the fin including a defect modification layer on a first semiconductor layer, a second semiconductor layer on the defect modification layer, and a third semiconductor layer on the second semiconductor layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

A fabrication method of a semiconductor substrate includes: performing a chemical mechanical polishing process on a silicon carbide wafer; and performing a heating process on the silicon carbide wafer to remove a naturally formed oxide layer, to remove contaminants, to obtain a scratch-free surface, and to planarize, wherein the heating process includes: heating a chamber of a furnace and the silicon carbide wafer to T degrees Celsius for a time t, and introducing hydrogen, argon, nitrogen, or/and hydrogen chloride into the chamber; and then cooling down the furnace.

Provided are a graphene structure and a method of forming the graphene structure. The graphene structure includes a substrate and graphene on a surface of the substrate. Here, a bonding region in which a material of the substrate and carbon of the graphene are covalently bonded is formed between the surface of the substrate and the graphene.

The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a groove formed on the substrate, a channel layer structure grown under restriction of the groove structure, the channel layer structure being exposed from an upper surface of the substrate; a barrier layer covering the exposed channel layer structure, a two-dimensional electron gas and a two-dimensional hole gas respectively formed on a second face and a first face of the channel layer structure, and a source, a gate, and a drain formed on the first face/second face of the channel layer structure, and a bottom electrode formed on the second face/first face of the channel layer structure. The semiconductor device can reduce the gate leakage current, has a high threshold voltage, high power, and high reliability, can achieve a low on-resistance and a normally off state of the device, and can provide a stable threshold voltage, such that the semiconductor device has good switching characteristics. Moreover, the local electric field intensity may be effectively reduced, and the overall performance and reliability of the device may be improved; and the structure and manufacturing process of the semiconductor device are relatively simple, which can effectively reduce the manufacturing cost.

Embodiments of the present disclosure relate to methods for forming a source/drain extension. In one embodiment, a method for forming an nMOS device includes forming a gate electrode and a gate spacer over a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to expose a side wall and a bottom, forming a silicon arsenide (Si:As) layer on the side wall and the bottom, and forming a source/drain region on the Si:As layer. During the deposition of the Si:As layer and the formation of the source/drain region, the arsenic dopant diffuses from the Si:As layer into a third portion of the semiconductor fin located below the gate spacer, and the third portion becomes a doped source/drain extension region. By utilizing the Si:As layer, the doping of the source/drain extension region is controlled, leading to reduced contact resistance while reducing dopants diffusing into the channel region.

Generally, examples described herein relate to methods and semiconductor processing systems for anisotropically epitaxially growing a material on a silicon germanium (SiGe) surface. In an example, a surface of silicon germanium is formed on a substrate. Epitaxial silicon germanium is epitaxially grown on the surface of silicon germanium. A first growth rate of the epitaxial silicon germanium is in a first direction perpendicular to the surface of silicon germanium, and a second growth rate of the epitaxial silicon germanium is in a second direction perpendicular to the first direction. The first growth rate is at least 5 times greater than the second growth rate.