Systems and methods disclosed and contemplated herein relate to manufacturing thin film semiconductors. Resulting thin film semiconductors are particularly suited for applications such as flexible optoelectronics and photovoltaic devices. Broadly, methods and techniques disclosed herein include high-temperature deposition techniques combined with lift-off in aqueous environments. These methods and techniques can be utilized to incorporate thin film semiconductors into substrates that have limited temperature tolerances.

A method of making an atomic layer nanoribbon that includes forming a double atomic layer ribbon having a first monolayer and a second monolayer on a surface of the first monolayer, wherein the first monolayer and the second monolayer each contains a transition metal dichalcogenide material, oxidizing at least a portion of the first monolayer to provide an oxidized portion, and removing the oxidized portion to provide an atomic layer nanoribbon of the transition metal dichalcogenide material. Also provided are double atomic layer ribbons, double atomic layer nanoribbons, and single atomic layer nanoribbons prepared according to the method.

A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.

A method for manufacturing a semiconductor device includes supplying a silicon-containing gas to a substrate having a recess formed in a surface of the substrate to deposit a silicon film in the recess, supplying, to the substrate, a first etching gas having a first etching profile in which an amount of etching for an upper portion of the recess in a depth direction and an amount of etching for a lower portion of the recess in the depth direction are different from each other, to etch the silicon film in the recess, supplying, to the substrate, a second etching gas having a second etching profile that is different from the first etching profile of the first etching gas to etch the silicon film in the recess, and additionally depositing the silicon film on the already deposited silicon film etched by the second etching gas.

A method for making a semiconductor device may include forming a semiconductor layer, and forming a superlattice adjacent the semiconductor layer and including stacked groups of layers. Each group of layers may include stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one oxygen monolayer of a given group of layers may comprise an atomic percentage of .sup.18O greater than 10 percent.

A III-nitride-based semiconductor device is provided. The III-nitride semiconductor device includes a silicon substrate having a surface with a periodic array of recesses formed therein. A discontinuous insulating layer is formed within each recess of the periodic array of recesses such that a portion of the silicon substrate surface between adjacent recesses is free from coverage of the discontinuous insulating layer. A first epitaxial III-nitride semiconductor layer is formed over the silicon substrate with the periodic array of recesses and discontinuous insulating layer formed thereon. A second III-nitride semiconductor layer is disposed over the first III-nitride semiconductor layer and has a bandgap greater than a bandgap of the first III-nitride semiconductor layer. At least one source and at least one drain are disposed over the second III-nitride semiconductor layer. A gate is also disposed over the second III-nitride semiconductor layer between the source and the drain.

A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement, and a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice. The first superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on the substrate. Subsequent a first period of time, the methods may include providing a germanium-containing precursor to the processing region of the semiconductor processing chamber. The methods may include thermally reacting the silicon-containing precursor and the germanium-containing precursor at a temperature greater than or about 400° C. The methods may include forming a silicon-and-germanium-containing layer on the substrate.

Techniques related to forming low defect density III-N films, device structures, and systems incorporating such films are discussed. Such techniques include epitaxially growing a first crystalline III-N structure within an opening of a first dielectric layer and extending onto the first dielectric layer, forming a second dielectric layer over the first dielectric layer and laterally adjacent to a portion of the first structure, and epitaxially growing a second crystalline III-N structure extending laterally onto a region of the second dielectric layer.

Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate and an insulator layer above the substrate. A channel area may include an III-V material relaxed grown on the insulator layer. A source area may be above the insulator layer, in contact with the insulator layer, and adjacent to a first end of the channel area. A drain area may be above the insulator layer, in contact with the insulator layer, and adjacent to a second end of the channel area that is opposite to the first end of the channel area. The source area or the drain area may include one or more seed components including a seed material with free surface. Other embodiments may be described and/or claimed.