A method of producing a reduced-defect density crystalline silicon film includes forming a Six1Ge1-x1 film on a substrate, forming a Six2Ge1-x2 film on the Six1Ge1-x1 film, forming a silicon film on the Six2Ge1-x2 film, and annealing to crystallize the Six1Ge1-x1, Six2Ge1-x2, and silicon films. The values of x1 and x2 are between zero and one. The Six1Ge1-x1 and Six2Ge1-x2 films are amorphous at formation, having a first thermal budget and a second thermal budget, respectively, for crystallization, the second thermal budget lower than the first thermal budget, the Six2Ge1-x2 film spaced apart from the substrate by the Six1Ge1-x1 film. A crystalline silicon TFT device includes a substrate, a crystallized Six1Ge1-x1 layer on the substrate, a crystallized Six2Ge1-x2 layer on the crystallized Six1Ge1-x1 layer, a crystallized silicon layer on the Six2Ge1-x2 layer, a gate insulator layer on the crystallized silicon layer, and a gate electrode on the gate insulator layer.

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a substrate; forming a silicon layer on the substrate, wherein an edge region of the top surface of the substrate is exposed from the silicon layer; epitaxially growing a GaN-based semiconductor material on the silicon layer and the substrate to form a GaN-based semiconductor layer on the silicon layer and a plurality of GaN-based nodules on the edge region of the top surface of the substrate; and performing a first dry etch step to remove the GaN-based nodules, wherein performing the first dry etch step includes applying a first bias power that is equal to or higher than 1500 W.

A method of producing a crystalline silicon film includes forming a first silicon film that is amorphous at formation, forming a doped film of silicon or germanium on the first silicon film, the doped film being amorphous at formation; and annealing the structure to crystallize the doped film and the first silicon film. A method of producing a crystalline silicon film includes forming a Si.sub.x1Ge.sub.1-x1 film on a substrate, forming a Si.sub.x2Ge.sub.1-x2 film on the Si.sub.x1Ge.sub.1-x1 film, the Si.sub.x1Ge.sub.1-x1 film being amorphous at formation and having a first thermal budget for crystallization, the Si.sub.x2Ge.sub.1-x2 film being amorphous at formation and having a second thermal budget for crystallization, the second thermal budget being lower than the first thermal budget, forming a silicon film on the Si.sub.x2Ge.sub.1-x2 film, the silicon film being amorphous at formation; and annealing to crystallize the Si.sub.x1Ge.sub.1-x1 film, the Si.sub.x2Ge.sub.1-x2 film, and the silicon film.

A substrate structure with high reflectance includes a base material, a patterned circuit layer, an insulating layer and a metal reflecting layer. The base material includes a first surface and a second surface opposite to the first surface. The patterned circuit layer is disposed on the first surface. The insulating layer covers the patterned circuit layer and a part of the first surface exposed by the patterned circuit layer. The metal reflecting layer covers the insulating layer, and a reflectance of the metal reflecting layer is substantially greater than or equal to 85%. A manufacturing method of a substrate structure with high reflectance is also provided.

A substrate structure with high reflectance includes a base material, a patterned circuit layer, an insulating layer and a metal reflecting layer. The base material includes a first surface and a second surface opposite to the first surface. The patterned circuit layer is disposed on the first surface. The insulating layer covers the patterned circuit layer and a part of the first surface exposed by the patterned circuit layer. The metal reflecting layer covers the insulating layer, and a reflectance of the metal reflecting layer is substantially greater than or equal to 85%. A manufacturing method of a substrate structure with high reflectance is also provided.

A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type and forming a first III-nitride layer coupled to the III-nitride substrate. The first III-nitride layer is characterized by a first dopant concentration and the first conductivity type. The method also includes forming a plurality of trenches within the first III-nitride layer and epitaxially regrowing a second III-nitride structure in the trenches. The second III-nitride structure is characterized by a second conductivity type. The method further includes forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions, and epitaxially regrowing a III-nitride gate layer in the recess regions. The III-nitride gate layer is coupled to the second III-nitride structure and the III-nitride gate layer is characterized by the second conductivity type.

A base material is provided. A first patterned circuit layer and a second patterned circuit layer are formed on a first surface and a second surface of the base material. A first insulation layer and a metal reflection layer are provided on the first patterned circuit layer and a portion of the first surface exposed by the first patterned circuit layer, wherein the metal reflection layer covers the first insulation layer, and a reflectance of the metal reflection layer is substantially greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer. A first ink layer is formed on the first insulation layer before the metal reflection layer is formed.

A member is provided which includes a silicon base substrate layer, a transition layer arranged over the silicon base substrate layer, and a gallium nitride (GaN) buffer layer arranged over the transition layer. The member further includes a gallium oxide layer. The member is beneficial for co-integration of ultra-wide-bandgap technology with wide bandgap technology, such as by using the gallium oxide layer with the gallium nitride buffer layer on cheap silicon substrates, such as the silicon base substrate layer. Therefore, the member provides access to establish the gallium nitride buffer layer (or gallium nitride) on the silicon base substrate layer (or silicon production lines) with improved thermal conductivity and higher electrical performance.

A single crystal semiconductor includes a strain compensation layer; an amorphous substrate disposed on the strain compensation layer; a lattice matching layer disposed on the amorphous substrate and including two or more single crystal layers; and a single crystal semiconductor layer disposed on the lattice matching layer, the lattice matching layer including a direction control film disposed on the amorphous substrate and including a single crystal structure, and a buffer layer including a material different from that of the direction control film, the buffer layer being disposed on the direction control film and including a single crystal structure.

A bulk acoustic wave resonator and a method of manufacturing the same are provided. The bulk acoustic wave resonator includes: a first carrier substrate; a barrier layer on a main surface of the first carrier substrate and configured to prevent an undesired conductive channel from being generated due to charge accumulation on the main surface; a buffer layer on a side of the barrier layer away from the first carrier substrate; a piezoelectric layer on a side of the buffer layer away from the barrier layer; a first electrode and a second electrode on opposite sides of the piezoelectric layer; a first passivation layer and a second passivation layer, respectively covering sidewalls of the first electrode and the second electrode; a dielectric layer between the first passivation layer and the buffer layer, wherein a first cavity is provided between the first passivation layer and the dielectric layer.