A method of forming a plurality of devices on an engineered substrate structure includes forming an engineered substrate by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core with a first adhesion shell, encapsulating the first adhesion shell with a barrier layer, forming a bonding layer on the barrier layer, and forming a substantially single crystal layer coupled to the bonding layer. The method further comprises forming a buffer layer coupled to the substantially single crystal layer, forming one or more epitaxial III-V layers on the buffer layer according to requirements associated with the plurality of devices, and forming the plurality of devices on the substrate by removing a portion of the one or more epitaxial III-V layers disposed between the plurality of devices and removing a portion of the buffer layer disposed between the plurality of devices.

A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory opening fill structures including a memory film and a vertical semiconductor channel are formed in the memory openings. The vertical semiconductor channels can include a III-V compound semiconductor channel material that is electrically connected to the III-V compound semiconductor layer. The substrate and at least a portion of the silicon oxide layer can be subsequently detached.

A method for forming a semiconductor device structure is provided. The method includes forming an n-type doped region in a semiconductor substrate and forming a semiconductor stack over the semiconductor substrate. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes introducing n-type dopants from the n-type doped region into the semiconductor stack during the forming of the semiconductor stack. The method further includes patterning the semiconductor stack to form a fin structure and forming a dummy gate stack to wrap around a portion of the fin structure. In addition, the method includes removing the dummy gate stack and the sacrificial layers to release multiple semiconductor nanostructures made up of remaining portions of the semiconductor layers. The method includes forming a metal gate stack to wrap around the semiconductor nanostructures.

A method for manufacturing a semiconductor substrate by forming an insulator film and a semiconductor single crystal layer on a surface of a silicon single crystal substrate to manufacture a semiconductor substrate having the semiconductor single crystal layer on the insulator film, the method including at least the steps of: forming a silicon nitride film having an epitaxial relationship with the silicon single crystal substrate on the surface of the silicon single crystal substrate as the insulator film by subjecting the silicon single crystal substrate to a heat treatment under a nitrogen gas-containing atmosphere; and forming the semiconductor single crystal layer on the silicon nitride film by epitaxial growth. This makes it possible to obtain a semiconductor substrate by simple method with high productivity at low cost even when the insulator film provided between the silicon single crystal substrate and the semiconductor single crystal layer is a silicon nitride film.

A method of forming an LED emitter includes: providing a III-nitride layer on a substrate (310), the III-nitride layer having a planar top surface; providing discrete lateral growth regions on the top surface; selectively epitaxially growing, on each discrete lateral growth region, a base region (1210) comprising an In(x)Ga(1-x)N material, each extending perpendicular to the top surface; providing surfaces of the In(x)Ga(1-x)N material on portions of the base regions (1210), the surfaces having a relaxed strain and being characterized by a base lattice constant within 0.1% of its bulk relaxed value; and epitaxially growing LED regions on the surfaces, the LED regions including light-emitting layers of In(y)Ga(1-y)N material that are pseudomorphic with the surfaces of the In(x)Ga(1-x)N material, and characterized by an active region (1240) lattice constant within 0.1% of the base lattice constant, wherein 0.05<x<0.2 and y>0.3.

Embodiments of the disclosure provide a method for manufacturing a semiconductor device. The method includes: providing a substrate having at least one trench; forming a first polysilicon layer in the trench, covering a sidewall and a bottom of the trench and not fully fills the trench; annealing the first polysilicon layer; and forming a second polysilicon layer at a region of the trench where the first polysilicon layer is not filled after annealing.

A maskless, patterned graphene film is produced through use of a tunable metal as a catalyst for graphene growth. The metal layer contains precisely defined textures that control the formation of the graphene film. Specifically, graphene growth can be controlled from F-LG (few layer graphene) down to 2-LG (2-layer graphene) and 1-LG (1-layer graphene). More than one texture can be created to form maskless patterns of graphene. Once the graphene layer(s) are grown, the film can be released from the metal and applied to any form and shape of rigid or flexible substrate for a variety of different applications where graphene cannot be normally grown directly.

A method includes: providing a layer of porous silicon carbide supported by a silicon carbide substrate; providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide; forming semiconductor devices in the layer of epitaxial silicon carbide; and separating the silicon carbide substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. The layer of porous silicon carbide includes dopants defining a resistivity of the layer of porous silicon carbide. The resistivity of the layer of porous silicon carbide is different from a resistivity of the silicon carbide substrate. Additional methods are described.

Methods and systems for forming structures including a superlattice of silicon-containing epitaxial layers using nanoparticles. Exemplary methods can include forming nanoparticles in situ and depositing the nanoparticles onto a substrate surface to thereby form the epitaxial layers.

A semiconductor substrate (1) according to an embodiment includes: a hexagonal SiC single crystal layer (13I); an SiC epitaxial growth layer (12E) disposed on an Si plane of an SiC single crystal layer (13I); and an SiC polycrystalline growth layer (18PC) disposed on a C plane opposite to the Si plane of the SiC single crystal layer (13I). The SiC single crystal layer (13I) includes a single crystal SiC thin layer (10HE) obtained by weakening the hydrogen ion implantation layer (10HI), and a phosphorus ion implantation layer (10PI). The phosphorus ion implantation layer (10PI) is disposed between the single crystal SiC thin layer (10HE) and the SiC polycrystalline growth layer (18PC). Consequently, the present disclosure provides a low-cost and high-quality semiconductor substrate and a fabrication method thereof.