Porous III-nitrides having controlled/tuned optical, electrical, and thermal properties are described herein. Also disclosed are methods for preparing and using such porous III-nitrides.

A method for forming a semiconductor device structure is provided. The method includes forming an n-type doped region in a semiconductor substrate and forming a semiconductor stack over the semiconductor substrate. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes introducing n-type dopants from the n-type doped region into the semiconductor stack during the forming of the semiconductor stack. The method further includes patterning the semiconductor stack to form a fin structure and forming a dummy gate stack to wrap around a portion of the fin structure. In addition, the method includes removing the dummy gate stack and the sacrificial layers to release multiple semiconductor nanostructures made up of remaining portions of the semiconductor layers. The method includes forming a metal gate stack to wrap around the semiconductor nanostructures.

Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

Provided is a field effect transistor including a gate insulating layer having a two-dimensional material. The field effect transistor may include a first channel layer; a second channel layer disposed on the first channel layer; a gate insulating layer disposed on the second channel layer; a gate electrode disposed on the gate insulating layer; a first electrode electrically connected to the first channel layer; and a second electrode electrically connected to the second channel layer. Here, the gate insulating layer may include an insulative, high-k, two-dimensional material.

A film forming method includes: forming a laminated film, in which an interface layer, a bulk layer, and a surface layer are laminated in this order, on a base; and crystallizing the laminated film, wherein the bulk layer is formed of a film that is easier to crystallize than the interface layer in crystallizing the laminated film, and wherein the surface layer is formed of a film that is easier to crystallize than the bulk layer in crystallizing the laminated film.

The invention relates to a process for the preparation of a semiconductor material comprising at least one entirely monocrystalline semiconductor layer, said process comprising the steps of preparation of the surface of a first substrate to receive a monocrystalline silicon layer; deposition by Plasma-Enhanced Chemical Vapor Deposition (PECVD) of a layer of monocrystalline silicon by epitaxial growth with a growth rate gradient on the silicon layer monocrystalline obtained in step (i); and epitaxial growth of a monocrystalline layer of a semiconductor material on the monocrystalline silicon layer obtained in step (ii), to thus obtain a material comprising at least one entirely monocrystalline semiconductor layer. The invention also relates to a multilayer material comprising a monocrystalline layer of semiconductor material.

A stacked structure may include a first material layer, a two-dimensional material layer on the first material layer, and a second material layer on the two-dimensional material layer. The two-dimensional material layer may include a plurality of holes that each expose a portion of the first material layer. The second material layer may be coupled to the first material layer through the plurality of holes.

Thin film transistors having a spin-on two-dimensional (2D) channel material are described. In an example, an integrated circuit structure includes a first device layer including a first two-dimensional (2D) material layer above a substrate. The first 2D material layer includes molybdenum, sulfur, sodium and carbon. A second device layer including a second 2D material layer is above the substrate. The second 2D material layer includes tungsten, selenium, sodium and carbon.

In certain examples, methods and semiconductor structures are directed to a method comprising steps of forming by monolithically integrating or seeding via polycrystalline diamond (PCD) particles on a GaN-based layer characterized as including GaN in at least a surface region of the GaN-based layer. After the step of seeding, the PCD particles are grown under a selected pressure to form a diamond layer section and to provide a semi-conductive structure that includes the diamond layer section integrated on or against the surface region of the GaN-based layer.

A III-nitride-based semiconductor wafer is provided that includes a substrate with a central region and a peripheral edge region. One or more intermediate layers may be optionally provided selected from a buffer layer, a seed layer, or a transition layer. A peripheral edge feature is formed in or on a peripheral edge region of the substrate or the transition layer, with one or more peripheral edge passivation layers or peripheral edge surface texturing. The peripheral edge feature extends only around the peripheral edge and not in the central region. One or more III-nitride-based layers is positioned over the central region. In the central region, the III-nitride layer is an epitaxial layer while in the peripheral edge region, it is a polycrystalline layer. Stress due to lattice mismatches and differences in the coefficient of thermal expansion between the III-nitride layer and the substrate is relieved, minimizing defects.