An epitaxial substrate for electronic devices, including: a Si-based substrate; an AlN initial layer provided on the Si-based substrate; and a buffer layer provided on the AlN initial layer, wherein the roughness Sa of the surface of the AlN initial layer on the side where the buffer layer is located is 4 nm or more. As a result, an epitaxial substrate for electronic devices, in which V pits in a buffer layer structure can be suppressed and longitudinal leakage current characteristics can be improved when an electronic device is fabricated therewith, is provided.

The present disclosure provides a fabrication of M-plane gallium nitride which is able to grow M-plane gallium nitride without the need of expensive substrates, such as LiAlO.sub.2, LiGaO.sub.2 or SiC. The fabrication of M-plane gallium nitride includes preparing a zinc oxide hexagonal prism having a growth face, and growing a gallium nitride layer on the growth face of the zinc oxide hexagonal prism. The growth face is an M-plane perpendicular to a direction of gravity.

An electronic device includes a substrate, a barrier film, and one of an electrically-conductive layer and a semiconductor layer. The barrier film is provided on the substrate. The barrier film contains an inorganic polymer compound and an organic matter. One of the electrically-conductive layer and the semiconductor layer is provided on the substrate with the barrier film in between.

A semiconductor substrate is provided. The semiconductor substrate includes a ceramic base, a seed layer, and a nucleation layer. The ceramic base has a front surface and a back surface, and the front surface is a non-flat surface. The seed layer is disposed on the front surface of the ceramic substrate. The nucleation layer is disposed on the seed layer.

A self-supporting substrate includes a first nitride layer grown by hydride vapor deposition method or ammonothermal method and comprising a nitride of one or more element selected from the group consisting of gallium, aluminum and indium; and a second nitride layer grown by a sodium flux method on the first nitride layer and comprising a nitride of one or more element selected from the group consisting of gallium, aluminum and indium. The first nitride layer includes a plurality of single crystal grains arranged therein and being extended between a pair of main faces of the first nitride layer. The second nitride layer includes a plurality of single crystal grains arranged therein and being extended between a pair of main faces of the second nitride layer. The first nitride layer has a thickness larger than a thickness of the second nitride layer.

There are provided a setting process configured to set in a chamber an aluminum nitride substrate in which a semiconductor layer is formed on a first principal plane, and an oxide film forming process configured to heat an inside of the chamber with a water molecule (H.sub.2O) being introduced in the chamber and to form an oxide film including an amorphous oxide film and/or a crystalline oxide film on a second principal plane located on an opposite side to the first principal plane of the aluminum nitride substrate.

Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.

The disclosed light emitting device includes an intermediate layer interposed between the light emitting semiconductor structure and the substrate. The light emitting semiconductor structure includes a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, wherein the active layer has a multi quantum well structure including at least one period of a pair structure of a quantum barrier layer including Al.sub.xGa.sub.(1-x)N (0<x<1) and a quantum well layer including Al.sub.yGa.sub.(1-y)N (0<x<y<1), and at least one of the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer includes AlGaN. The intermediate layer includes AlN and has a plurality of air voids formed in the AlN. At least some of the air voids are irregularly aligned and the number of the air voids is 10.sup.7 to 10.sup.10/cm.sup.2.

The present application provides an array substrate. The array substrate includes a base substrate; a light shielding layer on the base substrate; a metal oxide layer on a side of the light shielding layer distal to the base substrate; and an active layer on a side of the metal oxide layer distal to the base substrate. The metal oxide layer includes a metal oxide material. The light shielding layer includes amorphous silicon. An orthographic projection of the light shielding layer on the base substrate substantially overlaps with an orthographic projection of the active layer on the base substrate, and substantially overlaps with an orthographic projection of the metal oxide layer on the base substrate.

A base substrate includes a supporting substrate and a base crystal layer provided on a main face of the supporting substrate composed of a crystal of a group 13 nitride and having a crystal growth surface. The base crystal layer includes a raised part. A reaction product of a material of the supporting substrate and the crystal of the group 13 nitride, metal of a group 13 element and/or void is present between the raised part and supporting substrate.