A semiconductor device with a small variation in characteristics is provided. The semiconductor device includes a first insulator; a second insulator having an opening over the first insulator; a third insulator that has a first depressed portion and is provided inside the opening; a first oxide that has a second depressed portion and is provided inside the first depressed portion; a second oxide provided inside the second depressed portion; a first conductor and a second conductor that are electrically connected to the second oxide and are apart from each other; a fourth insulator over the second oxide; and a third conductor including a region overlapping with the second oxide with the fourth insulator therebetween. The second oxide includes a first region, a second region, and a third region sandwiched between the first region and the second region in a top view. The first conductor includes a region overlapping with the first region and the second insulator. The second conductor includes a region overlapping with the second region and the second insulator. The third conductor includes a region overlapping with the third region.

A plurality of vertical stacks may be formed over a substrate. Each of the vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode. A continuous active layer may be formed over the plurality of vertical stacks. A gate dielectric layer may be formed over the continuous active layer. The continuous active layer and the gate dielectric layer may be patterned into a plurality of active layers and a plurality of gate dielectrics. Each of the plurality of active layers laterally surrounds a respective one of the vertical stacks that are arranged along a first horizontal direction, and each of the plurality of gate dielectrics laterally surrounds a respective one of the active layers. Gate electrodes may be formed over the plurality of gate dielectrics.

A semiconductor die includes a semiconductor substrate and a transistor array disposed over the semiconductor substrate. The transistor array includes unit cells and spacers. The unit cells are disposed along rows of the transistor array extending in a first direction and columns of the transistor array extending in a second direction perpendicular to the first direction. The spacers encircle the unit cells. The unit cells include source contacts and drain contacts separated by interlayer dielectric material portions. First sections of the spacers contacting the interlayer dielectric material portions are thicker than second sections of the spacers contacting the source contacts and the drain contacts.

As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of high manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.

A multilayer structure of the present invention is a multilayer structure including a base substrate and a semiconductor film that is made of α-Ga.sub.2O.sub.3 or an α-Ga.sub.2O.sub.3-based solid solution and has a corundum crystal structure, the semiconductor film being disposed on the base substrate. The semiconductor film has an average film thickness of greater than or equal to 10 μm. The semiconductor film is convexly or concavely warped. An amount of warpage of the semiconductor film is 20 μm or greater and 64 μm or less.

A laminate contains a crystal substrate; a middle layer formed on a main surface of the crystal substrate, the middle layer comprising a mixture of an amorphous region in an amorphous phase and a crystal region in a crystal phase having a corundum structure mainly made of a first metal oxide; and a crystal layer formed on the middle layer and having a corundum structure mainly made of a second metal oxide, wherein the crystal region is an epitaxially grown layer from a crystal plane of the crystal substrate.

An embodiment semiconductor module includes a substrate, a heterogeneous thin film including a first semiconductor layer disposed on a first region of the substrate and a second semiconductor layer disposed on a second region of the substrate, a first semiconductor device disposed on the first semiconductor layer of the heterogeneous thin film, and a second semiconductor device disposed on the second semiconductor layer of the heterogeneous thin film, wherein one of the first semiconductor layer or the second semiconductor layer comprises gallium oxide (Ga.sub.2O.sub.3) and the other includes silicon (Si).

A transistor includes a first gate electrode, a composite channel layer, a first gate dielectric layer, and source/drain contacts. The composite channel layer is over the first gate electrode and includes a first capping layer, a crystalline semiconductor oxide layer, and a second capping layer stacked in sequential order. The first gate dielectric layer is located between the first gate electrode and the composite channel layer. The source/drain contacts are disposed on the composite channel layer.

A transistor device including source and drain electrodes, a fin structure extending between and contacting respective sidewalls of the source and drain electrodes, a semiconductor channel layer over the upper surface and side surfaces of the fin structure and including a first and second vertical portions over the side surfaces of the fin structure, and the first and second vertical portions of the semiconductor channel layer both contact the respective sidewalls of the source electrode and the drain electrode, a gate dielectric layer over the semiconductor channel layer, and a gate electrode over the gate dielectric layer. By forming the semiconductor channel layer over a fin structure extending between sidewalls of the source and drain electrodes, a contact area between the semiconductor channel and the source and drain electrodes may be increased, which may provide increased driving current for the transistor device without increasing the device size.

A wafer processing apparatus is configured to process a wafer by supplying mist to a surface of the wafer. The wafer processing apparatus includes a furnace in which the wafer is disposed, a gas supplying device configured to supply gas into the furnace, a mist supplying device configured to supply the mist into the furnace, and a controller. The controller is configured to execute a processing step by controlling the gas supplying device and the mist supplying device to supply the gas and the mist into the furnace, respectively. The controller is further configured to control the mist supplying device to stop supplying the mist into the furnace while controlling the gas supplying device to keep supplying the gas into the furnace when the processing step ends.