A method includes forming a 2-D material semiconductor layer over a substrate; forming source/drain electrodes covering opposite sides of the 2-D material semiconductor layer, while leaving a portion of the 2-D material semiconductor layer exposed by the source/drain electrodes; forming a first gate dielectric layer over the portion of the 2-D material semiconductor layer by using a physical deposition process; forming a second gate dielectric layer over the first gate dielectric layer by using a chemical deposition process, in which a thickness of the first gate dielectric layer is less than a thickness of the second gate dielectric layer; and forming a gate electrode over the second gate dielectric layer.

Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes an emitter and a collector comprised of a first two-dimensional material having a first conductivity type, and an intrinsic base comprised of a second two-dimensional material having a second conductivity type different than the first conductivity type. The intrinsic base is laterally positioned between the emitter and the collector.

A semiconductor device includes a substrate, a semiconductor structure suspending over the substrate and comprising a source region, a drain region, and a channel region disposed between the source region and the drain region. The channel region includes a doped two-dimensional (2D) material layer comprising a first portion on an upper surface of the channel region. The semiconductor device also includes an interfacial layer surrounding the channel region including the first portion of the doped 2D material layer, and and a gate electrode surrounding the interfacial layer.

A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.

An approach to forming a field-effect transistor device formed with a two-dimensional material. The field-effect transistor device includes a channel composed of the two-dimensional material on a substrate and a high-k gate dielectric on the channel and extending under a sidewall spacer and around the sidewall spacer. The field-effect transistor includes a metal gate that is inside the high-k gate dielectric and over the channel. The source/drain is on a portion the two-dimensional material on the substrate. The source/drain abuts the sidewall spacer and is composed of a bi-layer metal.

Disclosed herein are a method of forming a transition metal dichalcogenide thin film and a method of manufacturing a device including the same. The method of forming a transition metal dichalcogenide thin film includes: providing a substrate in a reaction chamber; depositing a transition metal dichalcogenide thin film on the substrate using a sputtering process that uses a transition metal precursor and a chalcogen precursor and is performed at a first temperature; and injecting the chalcogen precursor in a gas state and heat-treating the transition metal dichalcogenide thin film at a second temperature that is higher than the first temperature. The substrate may include a sapphire substrate, a silicon oxide (SiO.sub.2) substrate, a nanocrystalline graphene substrate, or a molybdenum disulfide (MoS.sub.2) substrate.

A tunneling device includes a first semiconductor portion disposed on a first oxide substrate, a second semiconductor portion disposed on the first semiconductor portion, and an intermediate layer disposed between the first semiconductor portion and second semiconductor portion. The intermediate layer is a natural oxide film obtained by naturally oxidizing one surface of the second semiconductor portion for a predetermined time.

Provided are a two-dimensional material structure, a semiconductor device including the two-dimensional material structure, and a method of manufacturing the semiconductor device. The two-dimensional material structure may include a first insulator including a first dielectric material; a second insulator on the first insulator and including a second dielectric material; a first two-dimensional material film on an exposed surface of the first insulator; and a second two-dimensional material film provided on an exposed surface of the second insulator. The first and second two-dimensional material films may include a two-dimensional material having a two-dimensional layered structure, and the second two-dimensional material film may include more layers of the two-dimensional material than the first two-dimensional material film.

Processes for forming Mo and W containing thin films, such as MoS.sub.2, WS.sub.2, MoSe.sub.2, and WSe.sub.2 thin films are provided. Methods are also provided for synthesizing Mo or W beta-diketonate precursors. Additionally, methods are provided for forming 2D materials containing Mo or W.

A method of performing heteroepitaxy comprises exposing a substrate to a carrier gas, a first precursor gas, a Group II/III element, and a second precursor gas, to form a heteroepitaxial growth of one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN on the substrate; wherein the substrate comprises one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN; wherein the carrier gas is H.sub.2, wherein the first precursor is HCl, the Group II/III element comprises at least one of Zn, Cd, Hg, Al, Ga, and In; and wherein the second precursor is one of AsH.sub.3 (arsine), PH.sub.3 (phosphine), H.sub.2Se (hydrogen selenide), H.sub.2Te (hydrogen telluride), SbH.sub.3 (hydrogen antimonide), H.sub.2S (hydrogen sulfide), and NH.sub.3 (ammonia). The process may be an HVPE (hydride vapor phase epitaxy) process.