A method includes forming a protruding semiconductor stack including a plurality of sacrificial layers and a plurality of nanostructures, with the plurality of sacrificial layers and the plurality of nanostructures being laid out alternatingly. The method further includes forming a dummy gate structure on the protruding semiconductor stack, etching the protruding semiconductor stack to form a source/drain recess, and forming a source/drain region in the source/drain recess. The formation of the source/drain region includes growing first epitaxial layers. The first epitaxial layers are grown on sidewalls of the plurality of nanostructures, and a cross-section of each of the first epitaxial layers has a quadrilateral shape. The first epitaxial layers have a first dopant concentration. The formation of the source/drain region further includes growing a second epitaxial layer on the first epitaxial layers. The second epitaxial layer has a second dopant concentration higher than the first dopant concentration.

A film deposition method may include preparing a non-planar substrate including a first surface, a second surface, and an inclined surface between the first surface and the second surface; depositing a film having a thickness deviation on the first surface, the second surface, and the inclined surface; and etching the film deposited on the first surface, the second surface, and the inclined surface. A height of the second surface may be different than a height of the first surface.

Techniques for recovering the width of a top gate spacer in a field-effect transistor (FET) device are provided. In one aspect, a FET device includes: at least one gate; source/drain regions present on opposite sides of the at least one gate; gate spacers offsetting the at least one gate from the source/drain regions, wherein each of the gate spacers includes an L-shaped spacer alongside the at least one gate and a dielectric liner disposed on the L-shaped spacer; and at least one channel interconnecting the source/drain regions. A method of forming a FET device is also provided which includes recovering the width of the top gate spacer using the dielectric liner.

A method includes depositing a first semiconductor layer and a second semiconductor layer over a substrate; patterning the first semiconductor layer, the second semiconductor layer, and the substrate to form a first nanostructure, a second nanostructure, and a semiconductor fin; forming a recess in the first nanostructure and the second nanostructure, the recess exposing the semiconductor fin; epitaxially growing a first layer in the recess, a first portion of the first layer being disposed along a first sidewall of the first nanostructure, a second portion of the first layer being disposed along the semiconductor fin, the first portion of the first layer comprising two sidewalls extending toward a middle of the recess, the first portion of the first layer further comprising a first surface most distal from the first sidewall and directly interposed between the two sidewalls, the first portion being physically separated from the second portion; and epitaxially growing a second layer over the first portion of the first layer and over the second portion of the first layer, the second layer physically connecting the first portion of the first layer to the second portion of the first layer.

An integrated circuit includes a first nanostructure transistor having a first gate electrode and a second nanostructure transistor having a second gate electrode. A dielectric isolation structure is between the first and second gate electrodes. A gate connection metal is on a portion of the top surface of the first gate electrode and on a portion of a top surface of the second gate electrode. The gate connection metal is patterned to expose other portions of the top surfaces of the first and second gate electrodes adjacent to the dielectric isolation structure. A conductive via contacts the exposed portion of the top surface of the second gate electrode.

The present disclosure relates to the technical field of semiconductors. Disclosed is a multi-layer semiconductor material structure and a preparation method thereof, solving the problems of the existing semiconductor materials that have poor heat dissipation, high cost, and cannot be mass-produced. The multi-layer semiconductor material structure includes a highly thermally conductive support substrate and a crystallized device function layer, where the device function layer is provided on the highly thermally conductive support substrate, and has a single-crystal surface layer.

A two-dimensional semiconductor transistor includes a gate electrode, a gate insulating layer disposed on the gate electrode, an organic dopant layer disposed on the gate insulating layer and comprising an organic material including electrons, a two-dimensional semiconductor layer disposed on the organic dopant layer, a source electrode disposed on the two-dimensional semiconductor layer, and a drain electrode disposed on the two-dimensional semiconductor layer and spaced apart from the source electrode. A hysteresis of the two-dimensional semiconductor transistor is reduced due to the two-dimensional semiconductor transistor including the organic dopant layer.

A method includes providing a semiconductor substrate having a first region and a second region, epitaxially growing a semiconductor layer above the semiconductor substrate, patterning the semiconductor layer to form a first fin in the first region and a second fin in the second region, and depositing a dielectric material layer on sidewalls of the first and second fins. The method also includes performing an anneal process in driving dopants into the dielectric material layer, such that a dopant concentration in the dielectric material layer in the first region is higher than that in the second region, and performing an etching process to recess the dielectric material layer, thereby exposing the sidewalls of the first and second fins. A top surface of the recessed dielectric material layer in the first region is lower than that in the second region.

A method includes forming a fin protruding from a substrate, forming a first dielectric feature adjacent to the fin over the substrate, forming a cladding layer over the fin and the first dielectric feature, and removing a portion of the cladding layer to form an opening. The opening exposes the first dielectric feature. The method further includes forming a second dielectric feature adjacent to the cladding layer, the second dielectric feature filling the opening, forming a dummy gate stack over the fin and the second dielectric feature, forming source/drain (S/D) features in the fin adjacent to the dummy gate stack, and replacing the dummy gate stack and the cladding layer with a metal gate stack. The second dielectric feature divides the metal gate stack.

Semiconductor devices and methods are provided. In an embodiment, a semiconductor device includes first nanostructures directly over a first portion of a substrate and second nanostructures directly over a second portion of the substrate, n-type source/drain features coupled to the first nanostructures and p-type source/drain features coupled to the second nanostructures, and an isolation structure disposed between the first portion of the substrate and the second portion of the substrate. The isolation structure includes a first smiling region in direct contact with the first portion of the substrate and having a first height. The isolation structure also includes a second smiling region in direct contact with the second portion of the substrate and having a second height, the first height is greater than the second height.