A method includes forming a protruding semiconductor stack including a plurality of sacrificial layers and a plurality of nanostructures, with the plurality of sacrificial layers and the plurality of nanostructures being laid out alternatingly. The method further includes forming a dummy gate structure on the protruding semiconductor stack, etching the protruding semiconductor stack to form a source/drain recess, and forming a source/drain region in the source/drain recess. The formation of the source/drain region includes growing first epitaxial layers. The first epitaxial layers are grown on sidewalls of the plurality of nanostructures, and a cross-section of each of the first epitaxial layers has a quadrilateral shape. The first epitaxial layers have a first dopant concentration. The formation of the source/drain region further includes growing a second epitaxial layer on the first epitaxial layers. The second epitaxial layer has a second dopant concentration higher than the first dopant concentration.

A SiC epitaxial wafer includes a SiC substrate and an epitaxial layer laminated on the SiC substrate, wherein the epitaxial layer comprises a first layer, a second layer and a third layer in order from the SiC substrate side, the nitrogen concentration of the SiC substrate is 6.0×10.sup.18 cm.sup.−3 or more and 1.5×10.sup.19 cm.sup.−3 or less, the nitrogen concentration of the first layer is 1.0×10.sup.17 cm.sup.−3 or more and 1.5×10.sup.18 cm.sup.−3 or less, the nitrogen concentration of the second layer is 1.0×10.sup.18 cm.sup.−3 or more and 5.0×10.sup.18 cm.sup.−3 or less, and the nitrogen concentration of the third layer is 5.0×10.sup.13 cm.sup.−3 or more and 1.0×10.sup.17 cm.sup.−3 or less.

A semiconductor device includes a plurality of column portions including a semiconductor. The plurality of column portions each includes a source region, a drain region, and a channel formation region including a channel formed between the source region and the drain region. The semiconductor device further includes a gate electrode provided, via an insulating layer, at a side wall of the channel formation region, and also includes a first semiconductor layer provided at a side wall of the drain region. A conductive type of the first semiconductor layer differs from a conductive type of the semiconductor included in the drain region.

A method and apparatus for forming a super-lattice structure on a substrate is described herein. The super-lattice structure includes a plurality of silicon-germanium layers and a plurality of silicon layers disposed in a stacked pattern. The methods described herein produce a super-lattice structure with transition width of less than about 1.4 nm between each of the silicon-germanium layers and an adjacent silicon layer. The methods described herein include flowing one or a combination of a silicon containing gas, a germanium containing gas, and a halogenated species.

In a method of manufacturing a semiconductor device, a first fin structure, a second fin structure, a first wall fin structure and a second wall fin structure are formed over a substrate. The first and second fin structures are disposed between the first and second wall fin structures, and lower portions of the first and second fin structures and the first and second wall fin structures are embedded in the isolation insulating layer and upper portions thereof are exposed from the isolation insulating layer. A sidewall spacer layer is formed on sidewalls of the first and second fin structures. Source/drain regions of the first and second fin structures are recessed. An epitaxial source/drain structure is formed over the recessed first and second fin structures. A width W1 of the first and second fin structures is smaller than a thickness W2 of the sidewall spacer layer.

A multilayer structure of the present invention is a multilayer structure including a base substrate and a semiconductor film that is made of α-Ga.sub.2O.sub.3 or an α-Ga.sub.2O.sub.3-based solid solution and has a corundum crystal structure, the semiconductor film being disposed on the base substrate. The semiconductor film has an average film thickness of greater than or equal to 10 μm. The semiconductor film is convexly or concavely warped. An amount of warpage of the semiconductor film is 20 μm or greater and 64 μm or less.

A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.

A method of forming a germanium antimony tellurium (GeSbTe) layer includes forming a germanium antimony (GeSb) layer by repeatedly performing a GeSb supercycle; and forming the GeSbTe layer by performing a tellurization operation on the GeSb layer, wherein the GeSb supercycle includes performing at least one GeSb cycle; and performing at least one Sb cycle, the GeSbTe has a composition of Ge.sub.2Sb.sub.2+aTe.sub.5+b, in which a and b satisfy the following relations: −0.2<a<0.2 and −0.5<b<0.5.

A method of forming regrown fiducials includes providing a III-V compound substrate having a device region and an alignment mark region. The III-V compound substrate is characterized by a processing surface. The method also includes forming a hardmask layer having a first set of openings in the device region exposing a first surface portion of the processing surface of the III-V compound substrate and a second set of openings in the alignment mark region exposing a second surface portion of the processing surface and etching the first surface portion and the second surface portion of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches. The method also includes epitaxially regrowing a semiconductor layer in the trenches to form the regrown fiducials extending to a predetermined height over the processing surface in the alignment mark region.

A semiconductor device includes a channel layer configured to include a first nitride semiconductor containing gallium (Ga) and a first crystal dislocation density, and a barrier layer provided over a first surface side of the channel layer, and configured to include a second nitride semiconductor containing aluminum (Al) and a second crystal dislocation density, wherein the second crystal dislocation density is larger than the first crystal dislocation density.