An object of the present invention is to provide a novel technique capable of suppressing the occurrence of cracks in the growth layer.

The present invention is a method for manufacturing a semiconductor substrate, which includes: an embrittlement processing step S10 of reducing strength of an underlying substrate 10; and a crystal growth step S20 of forming the growth layer 20 on the underlying substrate 10. In addition, the present invention is a method for suppressing the occurrence of cracks in the growth layer 20, and this method includes an embrittlement processing step S10 of reducing the strength of the underlying substrate 10 before forming the growth layer 20 on the underlying substrate 10.

In a semiconductor device in which a channel formation region is included in an oxide semiconductor layer, an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer are used to supply oxygen of the gate insulating film, which is introduced by an ion implantation method, to the oxide semiconductor layer.

Ion species are supplied to a workpiece comprising a pattern layer over a substrate. A material layer is deposited on the pattern layer using an implantation process of the ion species. In one embodiment, the deposited material layer has an etch selectivity to the pattern layer. In one embodiment, a trench is formed on the pattern layer. The trench comprises a bottom and a sidewall. The material layer is deposited into the trench using the ion implantation process. The material layer is deposited on the bottom of the trench in a direction along the sidewall.

Favorable electrical characteristics are provided to a semiconductor device, or a semiconductor device with high reliability is provided. A semiconductor device including a bottom-gate transistor with a metal oxide in a semiconductor layer includes a source region, a drain region, a first region, a second region, and a third region. The first region, the second region, and the third region are each sandwiched between the source region and the drain region along the channel length direction. The second region is sandwiched between the first region and the third region along the channel width direction, the first region and the third region each include the end portion of the metal oxide, and the length of the second region along the channel length direction is shorter than the length of the first region or the length of the third region along the channel length direction.

The present document discloses a semiconductor device structure (1) comprising a SiC substrate (11), an In.sub.x1Al.sub.y1Ga.sub.1−x1−y1N buffer layer (13), wherein x1=0−1, y1=0−1 and x1+y1=1, and an In.sub.x2Al.sub.y2Ga.sub.1−x2−y2N nucleation layer (12), wherein x2=0−1, y2=0−1 and x2+y2=1, sandwiched between the SiC substrate (11) and the buffer layer (13). The buffer layer (13) presents a rocking curve with a (102) peak having a FWHM below 250 arcsec, and the nucleation layer (12) presents a rocking curve with a (105) peak having a FWHM below 200 arcsec, as determined by X-ray Diffraction (XRD).

Methods of making such a semiconductor device structure are disclosed.

A an apparatus includes a processing chamber configured to house a workpiece, a target holder in the processing chamber, a first magnetic element positioned over a backside of the target holder, a first arm assembly connected to the first magnetic element, a rotational shaft, and a first hinge mechanism connecting the rotational shaft and the first arm assembly.

A novel sputtering apparatus capable of separating functions can be provided. A sputtering apparatus is capable of forming a semiconductor film and includes a first target, a first power source connected to the first target, a first shutter facing the first target, a first driver portion connected to the first shutter, a second target, a second power source connected to the second target, a second shutter facing the second target, and a second driver portion connected to the second shutter. The first driver portion and the second driver portion operate in conjunction with each other.

The present disclosure provides a film forming method and an aluminum nitride film forming method for a semiconductor device. The film forming method for a semiconductor device includes performing multiple sputtering routes sequentially. Each sputtering routes includes: loading a substrate into a chamber; moving a shielding plate between a target and the substrate; introducing an inert gas into the chamber to perform a surface modification process on the target; performing a pre-sputtering to pre-treat a surface of the target; moving the shielding plate away from the substrate, and performing a main sputtering on the substrate to form a film on the substrate; and moving the substrate out of the chamber.

A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

An additive-containing aluminium nitride film containing an additive element selected from Sc, Y or Er is plasma etched through a mask for a period of time, t, with a plasma formed in a gaseous atmosphere having an associated gas pressure while an RF bias power is applied to the additive-containing aluminium nitride film. The gas pressure is reduced and/or the RF bias power is increased for a majority of the period of time t, so that the plasma etching becomes less chemical and more physical over a majority of the period of time, t.