A method includes providing a first layer of epitaxial silicon carbide supported by a silicon carbide substrate, providing a second layer of epitaxial silicon carbide on the first layer, forming a plurality of semiconductor devices in the second layer, and separating the substrate from the second layer at the first layer. The first layer includes a plurality of voids.

A semiconductor device and a method of forming the same are provided. A method includes forming a gate over a semiconductor structure. An epitaxial source/drain region is formed adjacent the gate. A dielectric layer is formed over the epitaxial source/drain region. An opening extending through the dielectric layer and exposing the epitaxial source/drain region is formed. A conductive material is non-conformally deposited in the opening. The conductive material fills the opening in a bottom-up manner.

A semiconductor layer is etched into a plurality of fin structures. A first nitridation process is performed to side surfaces of the fin structures. The first nitridation process forms a first oxynitride layer at the side surfaces of the fin structures. A liner oxide layer is formed on the first oxynitride layer. An isolation structure is formed around the fin structures after the forming of the liner oxide layer.

According to one embodiment, a method for manufacturing a substrate is disclosed. The method can include preparing a structure body. The structure body includes a first semiconductor member and a second semiconductor member. The first semiconductor member includes silicon carbide including a first element. The second semiconductor member includes silicon carbide including a second element. The first element includes at least one selected from a first group consisting of N, P, and As. The second element includes at least one selected from a second group consisting of B, Al, and Ga. The method can include forming a hole that extends through the second semiconductor member and reaches the first semiconductor member. In addition, the method can include forming a third semiconductor member in the hole. The third semiconductor member includes silicon carbide including a third element. The third element includes at least one selected from the first group.

Fabricating a regrown GaN p-n junction includes depositing a n-GaN layer on a substrate including n.sup.+-GaN, etching a surface of the n-GaN layer to yield an etched surface, depositing a p-GaN layer on the etched surface, etching a portion of the n-GaN layer and a portion of the p-GaN layer to yield a mesa opposite the substrate, and passivating a portion of the p-GaN layer around an edge of the mesa. The regrown GaN p-n junction is defined at an interface between the n-GaN layer and the p-GaN layer. The regrown GaN p-n junction includes a substrate, a n-GaN layer on the substrate having an etched surface, a p-GaN layer on the etched surface, a mesa defined by an etched portion of the n-GaN layer and an etched portion of the p-GaN layer, and a passivated portion of the p-GaN layer around an edge of the mesa.

A semiconductor device may include a semiconductor layer; a source electrode disposed above one main surface of the semiconductor layer; a drain electrode disposed below another main surface of the semiconductor layer; and an insulation gate section. The semiconductor layer may include a drift region of a first conductivity type; a JFET region of the first conductivity type disposed above the drift region; a body region of a second conductivity type disposed above the drift region and adjoining the JFET region; and a source region of the first conductivity type separated from the JFET region by the body region. The insulation gate section may be opposed to a portion of the body region that separates the JFET region and the source region, a space may be provided within the semiconductor layer, and the drift region, the JFET region and the body region may be exposed to the space.

The invention provides a method of manufacturing a SiC epitaxial wafer in which stacking faults are less likely to occur when a current is passed in a forward direction. The method of manufacturing the SiC epitaxial wafer includes a measurement step for measuring a basal plane dislocation density, a layer structure determining process for determining the layer structure of the epitaxial layer, and an epitaxial growth step for growing the epitaxial layers. And in the layer structure determination step, in the case of (i) when the basal plane dislocation density is lower than a predetermined value, the epitaxial layer includes a conversion layer and a drift layer from the SiC substrate side; and in the case of (ii) when the density is equal to or higher than the predetermined value, the epitaxial layer includes a conversion layer, a recombination layer, and a drift layer from the SiC substrate side.

Described herein is a technique capable of stabilizing conditions in a furnace at the start of a film-forming process. According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including: pre-processing of preparing a process environment in a process furnace of a substrate processing apparatus; film-forming by processing a substrate; and post-processing, wherein the pre-processing comprises (a1) determining whether to execute a maintenance recipe for a target object in the substrate processing apparatus, wherein (a1) is performed first in the pre-processing.

A semiconductor wafer includes a silicon carbide wafer and an epitaxial layer, which is disposed at a surface of the silicon carbide wafer and made of silicon carbide. The semiconductor wafer satisfies a condition that a waviness value is equal to or smaller than 1 micrometer. The waviness value is a sum of an absolute value of a value and an absolute value of a value . A highest height among respective heights of a plurality of points with reference to a surface reference plane within a light exposure area is denoted as the value . A lowest height among the respective heights of the points at the epitaxial layer with reference to the surface reference plane within the light exposure area is denoted as the value .

A group III nitride single crystal substrate including a main surface, the main surface including: a center; a periphery; an outer region whose distance from the center is greater than 30% of a first distance, the first distance being a distance from the center to the periphery; and an inner region whose distance from the center is no more than 30% of the first distance, wherein a ratio (v.sub.Av.sub.B)/v.sub.B is within the range of 0.1%, wherein v.sub.A is a minimum value of peak wave numbers of micro-Raman spectra in the inner region; and v.sub.B is an average value of peak wave numbers of micro-Raman spectra in the outer region.