A plasma stabilization method and a deposition method using the same are disclosed. The plasma stabilization method includes (a) supplying a source gas and (b) supplying a purge gas. The method may also include (c) supplying a reactive gas and (d) supplying plasma. The purge gas and the reactive gas are continuously supplied into a reactor during (a) through (d), and the plasma stabilization method is performed in a state where no substrate exists in the reactor.

A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.

Provided is a method of producing an epitaxial silicon wafer, which is excellent in productivity and prevents the formation of a backside haze in consecutive single-wafer processing epitaxial growth procedures on a plurality of silicon wafers without cleaning a process chamber after each epitaxial growth procedure. The method of producing an epitaxial silicon wafer includes: a step of loading a silicon wafer; a step of forming a silicon epitaxial layer; a step of unloading the silicon wafer; and a cleaning step. The cleaning step is performed before and after repeating a predetermined number of times a series of growth procedures including the silicon wafer loading step, the silicon epitaxial layer formation step, and the silicon wafer unloading step.

The present invention provides an optimizing growth method for improving quality of MOCVD epitaxial thin films, including the following method: step 1, putting a substrate and a thin film A to a reaction chamber of an MOCVD equipment; and feeding a compound containing an element X as an X source under the condition that the reaction chamber is filled with H2; configuring a temperature, reaction chamber pressure and deposition time within a parameter range where the gaseous compound can decompose X atoms; pre-depositing an X atomic layer on a surface of the substrate or the thin film A; the X atomic layer is adsorbed on the substrate or thin film A at this time; and the X atomic layer can be reacted with other compounds to generate a thin film B component in the follow-up process, or can directly form a thin film B component with the thin film A.

Methods for fabricating semiconductor devices include forming a fin-type pattern protruding on a substrate, forming a gate electrode intersecting the fin-type pattern, forming a first recess adjacent to the gate electrode and within the fin-type pattern by using dry etching, forming a second recess by treating a surface of the first recess with a surface treatment process including a deposit process and an etch process, and forming an epitaxial pattern in the second recess.

Embodiments of this disclosure include apparatus, systems, and methods for fabricating monolayers. In one example, a method includes forming a multilayer film having a plurality of monolayers of a two-dimensional (2D) material on a growth substrate. The multilayer film has a first side proximate the growth substrate and a second side opposite the first side.

A method includes etching a hybrid substrate to form a recess in the hybrid substrate, in which the hybrid substrate includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the first semiconductor layer, in which after the etching, a top surface of the first semiconductor layer is exposed to the recess; forming a spacer on a sidewall of the recess, in which the spacer is slanted at a first angle relative to a top surface of the first semiconductor layer; reshaping the spacer such that the a first sidewall of the reshaped spacer is slanted at a second angle relative to the top surface of the first semiconductor layer, in which the second angle is greater than the first angle; and performing a first epitaxy process to grow an epitaxy semiconductor layer in the recess after reshaping the spacer.

The present disclosure describes an exemplary fin structure formed on a substrate. The disclosed fin structure comprises an n-type doped region formed on a top portion of the substrate, a silicon epitaxial layer on the n-type doped region, and an epitaxial stack on the silicon epitaxial layer, wherein the epitaxial stack comprises a silicon-based seed layer in physical contact with the silicon epitaxial layer. The fin structure can further comprise a liner surrounding the n-type doped region, and a dielectric surrounding the liner.

A method of manufacturing a thin film transistor includes: removing an oxide film on a surface of an amorphous silicon layer by performing a surface cleaning; and forming an active layer by performing a heat treatment on the amorphous silicon layer, where the amorphous silicon layer is changed into crystalline silicon by the heat treatment.

An integrated microwave photonics (IMWP) apparatus is provided using sapphire as a platform. The IMWP apparatus includes: a sapphire substrate having a step-terrace surface; and a III-V stack layer epitaxially grown on the sapphire substrate. The III-V stack layer includes: a first III-V layer disposed on the sapphire substrate; a low temperature (LT) III-V buffer layer disposed on the first III-V layer; multiple second III-V layers disposed and stacked on the LT III-V buffer layer; a third III-V layer disposed on the second III-V layers; a III-V quantum well layer disposed on the third III-V layers; and a fourth III-V layer disposed on the III-V quantum well layer. The second III-V layers are respectively annealed. A growth temperature of the LT III-V layer and a growth temperature of the III-V quantum well layer are lower than a growth temperature of each of the first, second, third and fourth III-V layers.