A semiconductor device and a method of manufacturing a semiconductor device according to one or more embodiments are disclosed. An interface layer is formed by implanting ionized impurities into a first layer comprising single-crystalline silicon carbide (SiC). Surfaces of the interface layer and a second layer comprising polycrystalline silicon carbide (SiC) are activated. The activated surfaces of the interface layer and the second layer are contacted and bonded. A covering layer is formed to cover a top surface and sides of the first layer, sides of the interface layer, and sides of the second layer.

In one embodiment, a method of manufacturing a semiconductor device includes forming a first semiconductor layer including impurity atoms with a first density, on a first substrate, forming a second semiconductor layer including impurity atoms with a second density higher than the first density, on the first semiconductor layer, and forming a porous layer resulting from porosification of at least a portion of the second semiconductor layer. The method further includes forming a first film including a device, on the porous layer, providing a second substrate provided with a second film including a device, and bonding the first and second substrates to sandwich the first and second films. The method further includes separating the first and second substrates from each other such that a first portion of the porous layer remains on the first substrate and a second portion of the porous layer remains on the second substrate.

A system and method for etching workpieces in a uniform manner are disclosed. The system includes a semiconductor processing system that generates a ribbon ion beam, and a workpiece holder that scans the workpiece through the ribbon ion beam. The workpiece holder includes a plurality of independently controlled thermal zones so that the temperature of different regions of the workpiece may be separately controlled. In certain embodiments, etch rate uniformity may be a function of distance from the center of the workpiece, also referred to as radial non-uniformity. Further, when the workpiece is scanned, there may also be etch rate uniformity issues in the translated direction, referred to as linear non-uniformity. The present workpiece holder comprises a plurality of independently controlled thermal zones to compensate for both radial and linear etch rate non-uniformity.

A seed crystal layer is provided on a supporting body. A laser light is irradiated from a side of the supporting body to provide an altered portion along an interface between the supporting body and seed crystal layer. The altered layer is composed of a nitride of a group 13 element and comprising a portion into which dislocation defects are introduced or an amorphous portion.

In one embodiment, an integrated circuit includes a substrate, a buffer layer, a source region, a drain region, a channel region, and a gate structure. The substrate includes silicon. The buffer layer is above the substrate and includes a semiconductor material having defects near an interface with the substrate. The buffer layer also includes ions implanted among the defects. The source region and drain region are above the buffer layer, and the channel region is above the buffer layer and between the source and drain regions. The gate structure above the channel region.

The present document discloses a semiconductor device structure (1) comprising a SiC substrate (11), an In.sub.x1Al.sub.y1Ga.sub.1−x1−y1N buffer layer (13), wherein x1=0−1, y1=0−1 and x1+y1=1, and an In.sub.x2Al.sub.y2Ga.sub.1−x2−y2N nucleation layer (12), wherein x2=0−1, y2=0−1 and x2+y2=1, sandwiched between the SiC substrate (11) and the buffer layer (13). The buffer layer (13) presents a rocking curve with a (102) peak having a FWHM below 250 arcsec, and the nucleation layer (12) presents a rocking curve with a (105) peak having a FWHM below 200 arcsec, as determined by X-ray Diffraction (XRD).

Methods of making such a semiconductor device structure are disclosed.

Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

A method for manufacturing a semiconductor device is provided, including forming a fin field effect transistor (FinFET) structure on a semiconductor substrate. The FinFET structure includes at least one fin, and a gate electrode structure and source/drain regions on the at least one fin. A dielectric film is formed over the at least on fin. The dielectric film is irradiated with ultra violet (UV) radiation from a single UV source.

There is provided a method of manufacturing a group III nitride semiconductor substrate including: a fixing step S10 of fixing abase substrate, which includes a group III nitride semiconductor layer having a semipolar plane as a main surface, to a susceptor; a first growth step S11 of forming a first growth layer by growing a group III nitride semiconductor over the main surface of the group III nitride semiconductor layer in a state in which the base substrate is fixed to the susceptor using an HVPE method; a cooling step S12 of cooling a laminate including the susceptor, the base substrate, and the first growth layer; and a second growth step S13 of forming a second growth layer by growing a group III nitride semiconductor over the first growth layer in a state in which the base substrate is fixed to the susceptor using the HVPE method.

A method for forming a material having a Perovskite single crystal structure includes alternately growing, on a substrate, each of a plurality of first layers and each of a plurality of second layers having compositions different from the plurality of first layers and forming a material having a Perovskite single crystal structure by annealing the plurality of first layers and the plurality of second layers.