This semiconductor device according to an embodiment includes: a silicon carbide layer; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration not less than 1×10.sup.21cm.sup.−3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has its peak in the region, and a state density Z.sub.1/2 in a portion is not more than 1×10.sup.11cm.sup.−3. The portion is within 100 nm from the silicon oxide layer toward the silicon carbide layer. A nitrogen concentration and a carbon concentration in a position 1 nm from the peak toward the silicon oxide layer is not more than 1×10.sup.18cm.sup.−3, and a nitrogen concentration in a position 1 nm from the peak toward the silicon carbide layer is not more than 1×10.sup.18cm.sup.−3.

SiC Schottky rectifier 100 with surge current ruggedness. As referenced above, the Schottky rectifier 100 may be configured to provide multiple types of surge current protection.

A semiconductor component includes: gate structures extending from a first surface into an SiC semiconductor body; a drift zone of a first conductivity type formed in the SiC semiconductor body; first mesas and second mesas arranged between the gate structures in the SiC semiconductor body; body areas of a second conductivity type arranged in the first mesas and the second mesas, the body areas each adjoining a first side wall of one of the gate structures; first shielding areas of the second conductivity type adjoining a second side wall of one of the gate structures; second shielding areas of the second conductivity type adjoining the body areas in the second mesas; and diode areas of the conductivity type of the drift zone, the diode areas forming Schottky contacts with a load electrode between the first shielding areas and the second shielding areas.

A self-aligning process method and a self-aligning process apparatus for reducing critical dimension variation of a SiC trench gate MOSFET structure are disclosed.

A silicon carbide semiconductor device has a silicon carbide semiconductor substrate of a first conductivity type1, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, trenches, gate insulating films, gate electrodes, a first electrode, and a second electrode. The second semiconductor layer has a second semiconductor region of a second conductivity type, an impurity concentration of the second semiconductor region increases in the depth direction, has a maximum value at a predetermined depth, and from the predetermined depth, in the depth direction, decreases; a half-width of the impurity concentration is 0.15 μm or less; and an impurity concentration of the plurality of first semiconductor regions is constant in the depth direction.

Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.

A silicon carbide MOSFET device and method for making thereof are disclosed. The silicon carbide MOSFET device comprises a substrate heavily doped with a first conductivity type and an epitaxial layer lightly doped with the first conductivity type. A body region of a second conductivity type opposite the first is formed in epitaxial layer and an accumulation mode region of the first conductivity type is formed in the body region and an inversion mode region of the second conductivity type formed in the body region. The accumulation mode region is located between the inversion mode region and a junction field effect transistor (JFET) region of the epitaxial layer.

An improved SiC trench MOSFET having first and second type gate trenches for formation of a gate electrode, and a grounded P-shield region under the gate electrode for gate oxide electric-field reduction is disclosed. The gate electrodes are disposed into the first type gate trench having a thick oxide layer on trench bottom. The grounded P-shield region surrounding the second type gate trench filled up with the thick oxide layer is connected with a source metal through a grounded P region. The device further comprises a current spreading region surrounding the first type gate trench for on-resistance reduction.

A semiconductor wafer includes a first surface and an implantation area adjacent to the first surface and a certain distance away from the first surface, the implantation area including implanted particles and defects. A defect concentration in the implantation area deviates by less than 5% from a maximum defect concentration in the implantation area.

Implementations of a semiconductor device may include a trench including a gate and a gate oxide formed therein, the trench extending into a doped pillar of a first conductivity type formed in a substrate material. The device may include a trench channel adjacent to the trench and two doped pillars of a second conductivity type extending on each side of the first conductivity type doped pillar where a ratio of a depth of each of the two second conductivity type doped pillars to a depth of the trench into the substrate material may be at least 1.6 to 1.