An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.

Disclosed is a manufacturing method of a trench-type power device. The manufacturing method comprises: forming a drift region; forming a first trench and a second trench in the drift region; forming a gate stack in the first trench; forming a doped region and a well region of P type in the drift region by performing first ion implantation; forming a source region of N type in the well region by performing second ion implantation. The well region in which a dopant concentration gradually decreases with depth is formed by the first ion implantation, an upper part of the well region is inverted by the second ion implantation to form the source region. The doped region and well region can be formed by self-alignment in a common ion implantation step, improving power device performance, reducing numbers of process steps of ion implantation and masks, reducing manufacturing cost.

A silicon carbide semiconductor device, including a semiconductor substrate, and a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions and a plurality of fourth semiconductor regions formed in the semiconductor substrate. The semiconductor device further includes a plurality of trenches penetrating the second, third and fourth semiconductor regions, a plurality of gate electrodes respectively provided via a plurality of gate insulating films in the trenches, a plurality of fifth semiconductor regions each provided between one of the gate insulating films at the inner wall of one of the trenches, and the third semiconductor region and the fourth semiconductor region through which the one trench penetrates. The semiconductor device further includes first electrodes electrically connected to the second, third and fourth semiconductor regions, and a second electrode provided on a second main surface of the semiconductor substrate.

A silicon carbide semiconductor device includes: a body region of a second conductivity type provided on a drift layer of a first conductivity type; a source region of a first conductivity type provided on the body region; a source electrode connected to the source region; a gate insulating film provided on an inner surface of a trench; a gate electrode provided inside the trench with interposition of the gate insulating film; a protective layer of a second conductivity type provided below the gate insulating film; a connection layer of a second conductivity type being in contact with the protective layer and the body region; and an electric field relaxation layer of a second conductivity type being in contact with a bottom surface of the connection layer, provided below the connection layer, and having a lower impurity concentration of a second conductivity type than the connection layer.

P-type low-concentration regions face bottoms of trenches and extend in a longitudinal direction (first direction) of the trenches. The p-type low-concentration regions are adjacent to one another in a latitudinal direction (second direction) of the trenches and connected at predetermined locations by p-type low-concentration connecting portions that are scattered along the first direction and separated from one another by an interval of at least 3 μm. The p-type low-concentration regions and the p-type low-concentration connecting portions have an impurity concentration in a range of 3×10.sup.17/cm.sup.3 to 9×10.sup.17/cm.sup.3. A depth from the bottoms of the trenches to lower surfaces of the p-type low-concentration regions is in a range of 0.7 μm to 1.1 μm. Between the bottom of each of the trenches and a respective one of the p-type low-concentration regions, a p.sup.+-type high-concentration region is provided. Each p.sup.+-type high-concentration region has an impurity concentration that is at least 2 times the impurity concentration of the p-type low-concentration regions.

A method of manufacturing a silicon carbide substrate having a parallel pn layer. The method includes preparing a starting substrate containing silicon carbide, forming a first partial parallel pn layer on the starting substrate by a trench embedding epitaxial process, stacking a second partial parallel pn layer by a multi-stage epitaxial process on the first partial parallel pn layer, and stacking a third partial parallel pn layer on the second partial parallel pn layer by another trench embedding epitaxial process. Each of the first, second and third partial parallel pn layers is formed to include a plurality of first-conductivity-type regions and a plurality of second-conductivity-type regions alternately disposed in parallel to a main surface of the silicon carbide substrate. The first-conductivity-type regions of the first and third partial parallel pn layers face each other in a depth direction of the silicon carbide substrate, and the second-conductivity-type regions partial parallel pn layers face each other in the depth direction.

To provide a technique capable of improving performance and reliability of a semiconductor device. An n.sup.−-type epitaxial layer (12) is formed on an n-type semiconductor substrate (11), and a p.sup.+-type body region (14), n.sup.+-type current spreading regions (16, 17), and a trench. TR are formed in the n.sup.−-type epitaxial layer (12). A bottom surface B1 of the trench TR is located in the p.sup.+-type body region (14), a side surface S1 of the trench TR is in contact with the n.sup.+-type current spreading region (17), and a side surface S2 of the trench TR is in contact with the n.sup.+-type current spreading region (16). Here, a ratio of silicon is higher than a ratio of carbon in an upper surface T1 of the n.sup.−-type epitaxial layer (12), and the bottom surface B1, the side surface S1, and the side surface 32 of the trench. Furthermore, an angle θ1 at which the upper surface T1 of the n.sup.−-type epitaxial layer (12) is inclined with respect to the side surface S1 is smaller than an angle θ2 at which the upper surface T1 of the n.sup.−-type epitaxial layer (12) is inclined with respect to the side surface S2.

The present disclosure relates to: a MOSFET device which is applicable to a semiconductor device and, particularly, is manufactured using silicon carbide; and a manufacturing method therefor. The present disclosure provides a metal-oxide-semiconductor field effect transistor device which may comprise: a drain electrode; a substrate disposed on the drain electrode; an N-type drift layer disposed on the substrate; a plurality of P-type well layer regions disposed on the drift layer and spaced apart from each other to define a channel; an N+ region disposed on the well layer regions and adjacent to the channel; a P+ region disposed at the other side of the channel; a gate oxide layer disposed on the drift layer; a gate layer disposed on the gate oxide layer; and a source electrode disposed on the gate layer.

An improved SiC trench MOSFET having first and second type gate trenches for formation of a gate electrode, and a grounded P-shield region under the gate electrode for gate oxide electric-field reduction is disclosed. The gate electrodes are disposed into the first type gate trench having a thick oxide layer on trench bottom. The grounded P-shield region surrounding the second type gate trench filled up with the thick oxide layer is connected with a source metal through a grounded P region. The device further comprises a current spreading region surrounding the first type gate trench for on-resistance reduction.

Methods for fabricating SiC MOSFETs using channeled ion implants are disclosed. By aligning the workpiece such that the ions pass through channels in the SiC hexagonal crystalline structure, it is possible to achieve deeper implants than are otherwise possible. Further, it was found that these channeled implants can be tailored to achieve box-like dopant concentrations. This allows channeled ion implants to be used to create the current spreading layer of the MOSFET, which is conventional fabricated using epitaxial growth. Further, these channeled implants can also be used to create the shields between adjacent transistors. Additionally, the use of channeled implants allows a reduction in the number of epitaxially growth processes that are used to create super junction MOSFETs.