Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JEFT also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

A silicon carbide semiconductor device includes a silicon carbide (SiC) substrate having a SiC epitaxial layer disposed over a surface of the SiC substrate, the SiC substrate having a first conductivity and the SiC epitaxial layer having the first conductivity. A contact region and a well region are formed in the SiC epitaxial layer, the contact region and the well region have a doping level of a second conductivity opposite the first conductivity. The contact region lies completely within the well region, is not in contact with a region having the first conductivity and has edges recessed from edges of the well region.

A semiconductor device includes an SiC semiconductor layer which has a first main surface on one side and a second main surface on the other side, a semiconductor element which is formed in the first main surface, a raised portion group which includes a plurality of raised portions formed at intervals from each other at the second main surface and has a first portion in which some of the raised portions among the plurality of raised portions overlap each other in a first direction view as viewed in a first direction which is one of the plane directions of the second main surface, and an electrode which is formed on the second main surface and connected to the raised portion group.

A semiconductor device includes a first silicon carbide region of a first conductivity type, a second silicon carbide region of a second conductivity type on the first region, and a third silicon carbide region of a second conductivity type on the second region. Fourth and fifth silicon carbide region of the first conductivity type are on the third region. A first electrode has a first portion between the fourth region and fifth region in a first direction. A metal silicide layer is between the first portion and the third region, between the first portion and the fourth region in the first direction, and between the first portion and the fifth silicon carbide region in the first direction.

An insulated gate semiconductor device includes: a carrier transport layer of a first conductivity-type; an injection control region of a second conductivity-type; a carrier supply region of the first conductivity-type; a base contact region of the second conductivity-type; trenches penetrating the injection control region to reach the carrier transport layer; an insulated gate structure provided inside the respective trenches; an upper buried region of the second conductivity-type being in contact with a bottom surface of the injection control region; a lower buried region of the second conductivity-type being in contact with a bottom surface of the upper buried region and a bottom surface of the respective trenches; and a high-concentration region of the first conductivity-type provided inside the carrier transport layer to be in contact with a part of a bottom surface of the lower buried region.

An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.

Methods may include providing a device structure including a well formed in an epitaxial layer, and forming a plurality of shielding layers in the device structure, wherein at least one shielding layer is formed between a pair of adjacent sacrificial gates of a plurality of sacrificial gates. The method may further include forming a contact over the at least one shielding layer, forming a fill layer over the contact, and forming a plurality of trenches into the device structure, wherein at least one trench of the plurality of trenches is formed between a pair of adjacent shielding layers of the plurality of shielding layers, and wherein the at least one trench of the plurality of trenches is defined in part by a sidewall of the fill layer. The method may further include forming a gate structure within the at least one trench of the plurality of trenches.

A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

A silicon carbide semiconductor device includes an n-type drift layer disposed on an n-type silicon carbide substrate; an n-type current spreading layer disposed on a top surface of the drift layer, having a higher impurity concentration than the drift layer; a p-type base region disposed on a top surface of the current spreading layer; a p-type gate-bottom protection region located in the current spreading layer; a p-type base-bottom embedded region located in the current spreading layer, separated from the gate-bottom protection region to be in contact with a bottom surface of the base region; an insulated-gate electrode structure disposed in a trench penetrating the base region to reach the gate-bottom protection region, and a lower recombination region disposed in a lower portion of the drift layer, including crystal defects configured to recombine minority carriers injected into the drift layer.

The present disclosure provides a silicon carbide trench gate metal oxide semiconductor field effect transistor (MOSFET) and a method for manufacturing thereof. The silicon carbide trench gate MOSFET includes: a substrate having a first doping type, an epitaxial layer formed on the substrate and having the first doping type, an epitaxial well region formed above the epitaxial layer and having a second doping type, a first source contact region formed in the epitaxial well region and having the first doping type, a second source contact region formed in the epitaxial well region and having the second doping type, a trench gate, a source electrode and a drain electrode, wherein the trench gate includes a gate dielectric and a gate electrode, the silicon carbide trench gate MOSFET further includes a injection-type current diffusion region, which is wrapped around the bottom of the trench gate and has the first doping type.