A silicon carbide semiconductor substrate includes: a base substrate that has a main surface having an outer diameter of not less than 100 mm and that is made of single-crystal silicon carbide; an epitaxial layer formed on the main surface; and a deformation suppression layer formed on a backside surface of the base substrate opposite to the main surface. In this way, the deformation suppression layer suppresses the substrate from being deformed (for example, warped during high-temperature treatment). This can reduce a risk of causing defects such as crack in the silicon carbide semiconductor substrate during the manufacturing process in performing a method for manufacturing a silicon carbide semiconductor device using the silicon carbide semiconductor substrate.

A drift layer made of silicon carbide has a first conductivity type. A body region on the drift layer has a second conductivity type. A source region on the body region has the first conductivity type. A gate insulating film is on each inner wall of at least one trench. A protective layer has at least a portion below the trench, is in contact with the drift layer, and has the second conductivity type. A first low-resistance layer is in contact with the trench and the protective layer, straddles a border between the trench and the protective layer in the depth direction, has the first conductivity type, and has a higher impurity concentration than the drift layer. A second low-resistance layer is in contact with the first low-resistance layer, is away from the trench, has the first conductivity type, and has a higher impurity concentration than the first low-resistance layer.

A semiconductor device includes: a substrate; a drift region disposed on a principal surface of the substrate; a first well region extending from a second principal surface of the drift region in a direction perpendicular to the second principal surface and having a bottom portion; a second well region being in contact with the bottom portion and disposed at a portion inside the substrate located below the bottom portion; and a source region extending in a perpendicular direction from a region of the second principal surface provided with the first well region, and reaching the second well region. In a direction parallel to the second principal surface and oriented from a source electrode to a drain electrode, a distance of the second well region in contact with a gate insulating film is shorter than a distance of the first well region in contact with the gate insulating film.

A silicon carbide semiconductor device includes: a substrate; a drift layer over the substrate; a base region over the drift layer; multiple source regions over an upper layer portion of the base region; a contact region over the upper layer portion of the base region between opposing source regions; multiple trenches from a surface of each source region to a depth deeper than the base region; a gate electrode on a gate insulating film in each trench; a source electrode electrically connected to the source regions and the contact region; a drain electrode over a rear surface of the substrate; and multiple electric field relaxation layers in the drift layer between adjacent trenches. Each electric field relaxation layer includes: a first region at a position deeper than the trenches; and a second region from a surface of the drift layer to the first region.

A silicon carbide device includes a silicon carbide body with a trench gate structure that extends from a first surface into the silicon carbide body. A body region is in contact with an active sidewall of the trench gate structure. A source region is in contact with the active sidewall and located between the body region and the first surface. The body region includes a first body portion directly below the source region and distant from the active sidewall. In at least one horizontal plane parallel to the first surface, a dopant concentration in the first body portion is at least 150% of a reference dopant concentration in the body region at the active sidewall and a horizontal extension of the first body portion is at least 20% of a total horizontal extension of the body region.

A semiconductor device according to an embodiment includes: a silicon carbide layer having a first plane, a second plane facing the first plane, a first trench, a second trench, an n-type first silicon carbide region, a p-type second silicon carbide region between the first silicon carbide region and the first plane, an n-type third silicon carbide region between the second silicon carbide region and the first plane, and a p-type fourth silicon carbide region between the second trench and the first silicon carbide region; a gate electrode being located in the first trench; a gate insulating layer; a first electrode, a portion of the first electrode being located in the second trench; a second electrode; and an interlayer insulating layer being located between the gate electrode and the first electrode, in which an interface between the first electrode and the interlayer insulating layer is located in the first trench.

A structure of trench transistors includes the following elements. A substrate serves as a drain of the structure of trench transistors. An epitaxial layer is disposed on the substrate. A plurality of trenches are disposed in the epitaxial layer. A plurality of gate insulator layers are respectively disposed on the inner surfaces of the trenches. A plurality of gates are respectively disposed on the gate insulator layers. A plurality of first base regions are respectively disposed in the epitaxial layer between the adjacent trenches, and have a first depth from the top surface of the epitaxial layer. A plurality of second base regions are respectively disposed in the epitaxial layer adjacent to the sidewalls of the trenches, and each has a second depth from the bottom surface of the first base region. A plurality of sources are respectively disposed in the first base region beside the sidewalls of the trenches.

A semiconductor device of an embodiment includes a silicon carbide layer including first and second trenches, a first silicon carbide region of n-type, a second silicon carbide region of p-type disposed between the first trench and the second trench and having a depth deeper than depths of the first and second trenches, and a third silicon carbide region of n-type on the second silicon carbide region, a first gate electrode, a second gate electrode. The second silicon carbide region includes a first region of which a depth becomes deeper toward the second trench, and a second region of which a depth becomes deeper toward the first trench. In the second silicon carbide region, a first concentration distribution of a p-type impurity has a first concentration peak at a first position, and has a second concentration peak at a second position closer to the second trench than the first position.

A structure of trench transistors includes the following elements. A substrate serves as a drain of the structure of trench transistors. An epitaxial layer is disposed on the substrate. A plurality of trenches are disposed in the epitaxial layer. A plurality of gate insulator layers are respectively disposed on the inner surfaces of the trenches. A plurality of gates are respectively disposed on the gate insulator layers. A plurality of first base regions are respectively disposed in the epitaxial layer between the adjacent trenches, and have a first depth from the top surface of the epitaxial layer. A plurality of second base regions are respectively disposed in the epitaxial layer adjacent to the sidewalls of the trenches, and each has a second depth from the bottom surface of the first base region. A plurality of sources are respectively disposed in the first base region beside the sidewalls of the trenches.

The present invention relates to a semiconductor device having trench gates. The semiconductor device includes the following: a first semiconductor layer; a first semiconductor region selectively disposed in the upper layer of the first semiconductor layer; a second semiconductor region in contact with the first semiconductor region; a third semiconductor region on the bottom surfaces of the first and second semiconductor regions; gate trenches provided to penetrate the first and third semiconductor regions in the thickness direction of the first and third semiconductor regions to reach the inside of the first semiconductor layer; a field-reducing region on the bottom of each gate trench; and connection layers arranged in the first semiconductor layer at intervals so as to be each in contact with at least one of sidewalls of the gate trenches, the connection layers each electrically connecting the field-reducing region to the third semiconductor region.