A semiconductor device of an embodiment includes a silicon carbide layer including first and second trenches, a first silicon carbide region of n-type, a second silicon carbide region of p-type disposed between the first trench and the second trench and having a depth deeper than depths of the first and second trenches, and a third silicon carbide region of n-type on the second silicon carbide region, a first gate electrode, a second gate electrode. The second silicon carbide region includes a first region of which a depth becomes deeper toward the second trench, and a second region of which a depth becomes deeper toward the first trench. In the second silicon carbide region, a first concentration distribution of a p-type impurity has a first concentration peak at a first position, and has a second concentration peak at a second position closer to the second trench than the first position.

A semiconductor device according to an embodiment includes: a SiC layer having a first plane and a second plane facing the first plane, the SiC layer including a first trench on a first plane side, an n-type first SiC region, a p-type second SiC region, an n-type third SiC region located in this order from the second plane to the first plane, a p-type fourth SiC region between the first SiC region and the first trench, a fifth SiC region between the first SiC region and the first plane, and a sixth SiC region between the fourth SiC region and the fifth SiC region, and the sixth SiC region having an n-type impurity concentration higher than an n-type impurity concentration of the first SiC region; a gate electrode in the first trench; a first electrode on the first plane side; and a second electrode on a second plane side.

In an example, a substrate is oriented to a target axis, wherein a residual angular misalignment between the target axis and a preselected crystal channel direction in the substrate is within an angular tolerance interval. Dopant ions are implanted into the substrate using an ion beam that propagates along an ion beam axis. The dopant ions are implanted at implant angles between the ion beam axis and the target axis. The implant angles are within an implant angle range. A channel acceptance width is effective for the preselected crystal channel direction. The implant angle range is greater than 80% of a sum of the channel acceptance width and twofold the angular tolerance interval. The implant angle range is smaller than 500% of the sum of the channel acceptance width and twofold the angular tolerance interval.

A semiconductor device includes: a substrate; a drift region disposed on a principal surface of the substrate; a first well region extending from a second principal surface of the drift region in a direction perpendicular to the second principal surface and having a bottom portion; a second well region being in contact with the bottom portion and disposed at a portion inside the substrate located below the bottom portion; and a source region extending in a perpendicular direction from a region of the second principal surface provided with the first well region, and reaching the second well region. In a direction parallel to the second principal surface and oriented from a source electrode to a drain electrode, a distance of the second well region in contact with a gate insulating film is shorter than a distance of the first well region in contact with the gate insulating film.

A drift layer is made of silicon carbide and has a first conductivity type. At least one trench has a first side surface facing a Schottky barrier diode region, and a second side surface extending in a transistor region and contacting a source region, a body region, and the drift layer. A first protective region is provided under the at least one trench, has a second conductivity type, and is higher in impurity concentration of the second conductivity type than the body region. A second protective region extends from the first protective region, reaches at least one of the first side surface and an end region of the second side surface continuous with the first side surface, has an uppermost portion shallower than a lowermost portion of the body region, and is higher in impurity concentration of the second conductivity type than the body region.

A SiC Schottky rectifier with surge current ruggedness is described. The Schottky rectifier includes one or more multi-layer bodies that provide multiple types of surge current protection.

A wide band-gap semiconductor layer structure is provided that comprises a drift region having a first conductivity type and a plurality of source regions having the first conductivity type on the drift region. A plurality of trenches are provided in an upper surface of the wide band-gap semiconductor layer structure. Second conductivity type dopants are implanted into the wide band-gap semiconductor layer structure to simultaneously form well regions underneath the source regions and trench shielding regions underneath the trenches, the well regions and the trench shielding regions each having a second conductivity type.

A semiconductor device includes: a gate electrode groove formed in contact with a drift region, a well region, and a source region; a gate electrode formed on a surface of the gate electrode groove via an insulating film; a source electrode groove in contact with the gate electrode groove; a source electrode electrically connected to a source region; and a gate wiring electrically insulated from the source electrode and formed inside the source electrode groove in contact with the gate electrode.

A drift layer made of silicon carbide has a first conductivity type. A body region on the drift layer has a second conductivity type. A source region on the body region has the first conductivity type. A gate insulating film is on each inner wall of at least one trench. A protective layer has at least a portion below the trench, is in contact with the drift layer, and has the second conductivity type. A first low-resistance layer is in contact with the trench and the protective layer, straddles a border between the trench and the protective layer in the depth direction, has the first conductivity type, and has a higher impurity concentration than the drift layer. A second low-resistance layer is in contact with the first low-resistance layer, is away from the trench, has the first conductivity type, and has a higher impurity concentration than the first low-resistance layer.

A semiconductor device according to an embodiment includes: a silicon carbide layer having a first plane, a second plane facing the first plane, a first trench, a second trench, an n-type first silicon carbide region, a p-type second silicon carbide region between the first silicon carbide region and the first plane, an n-type third silicon carbide region between the second silicon carbide region and the first plane, and a p-type fourth silicon carbide region between the second trench and the first silicon carbide region; a gate electrode being located in the first trench; a gate insulating layer; a first electrode, a portion of the first electrode being located in the second trench; a second electrode; and an interlayer insulating layer being located between the gate electrode and the first electrode, in which an interface between the first electrode and the interlayer insulating layer is located in the first trench.