Techniques for joining dissimilar materials in microelectronics are provided. Example techniques direct-bond dissimilar materials at an ambient room temperature, using a thin oxide, carbide, nitride, carbonitride, or oxynitride intermediary with a thickness between 100-1000 nanometers. The intermediary may comprise silicon. The dissimilar materials may have significantly different coefficients of thermal expansion (CTEs) and/or significantly different crystal-lattice unit cell geometries or dimensions, conventionally resulting in too much strain to make direct-bonding feasible. A curing period at ambient room temperature after the direct bonding of dissimilar materials allows direct bonds to strengthen by over 200%. A relatively low temperature anneal applied slowly at a rate of 1° C. temperature increase per minute, or less, further strengthens and consolidates the direct bonds. The example techniques can direct-bond lithium tantalate LiTaO.sub.3 to various conventional substrates in a process for making various novel optical and acoustic devices.

A base substrate (1) for a group III-V compound crystal according to the present invention includes: a ceramic core layer (2); an impurity encapsulating layer (3) configured to encapsulate the ceramic core layer (2); a bonding layer (4) on the impurity encapsulating layer; and a processed layer (5) on the bonding layer. The impurity encapsulating layer (3) is a layer made of a composition represented by a composition formula SiOXNY (here, x=0 to 2, y=0 to 1.5, and x+y>0), the bonding layer (4) is a layer made of a composition represented by a composition formula SiO.sub.x′N.sub.y′ (here, x′=1 to 2, and y′=0 to 2, and the processed layer (5) is a seed crystal layer. According to the present invention, it is possible to provide the base substrate for a group III-V compound crystal and a method for producing the same for obtaining a group III-V compound crystal having a large diameter and high quality.

Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second substrate, with at least one of the first substrate and the second substrate having a plurality of solid-state transducers. The second substrate can include a plurality of projections and a plurality of intermediate regions and can be bonded to the first substrate with a discontinuous bond. Individual solid-state transducers can be disposed at least partially within corresponding intermediate regions and the discontinuous bond can include bonding material bonding the individual solid-state transducers to blind ends of corresponding intermediate regions. Associated methods and systems of discontinuous bonds for semiconductor devices are disclosed herein.

A method for bonding a first substrate with a second substrate at respective contact faces of the substrates with the following steps: holding the first substrate to a first sample holder surface of a first sample holder with a holding force F.sub.H1 and holding the second substrate to a second sample holder surface of a second sample holder with a holding force F.sub.H2; contacting the contact faces at a bond initiation point and heating at least the second sample holder surface to a heating temperature T.sub.H; bonding of the first substrate with the second substrate along a bonding wave running from the bond initiation point to the side edges of the substrates, wherein the heating temperature T.sub.H is reduced at the second sample holder surface during the bonding.

Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.

A method for bonding a first substrate to a second substrate on mutually facing contact surfaces of the substrates, wherein the first substrate is mounted on a first chuck and the second substrate is mounted on a second chuck, and wherein a plate is arranged between the second substrate and the second chuck, wherein the second substrate with the plate is deformed with respect to the second chuck before and/or during the bonding. Furthermore, the present invention relates to a corresponding device and a corresponding plate.

A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming a plurality of first transistors each including a single crystal channel; forming a first metal layer and a second metal layer, where the first level includes the plurality of first transistors, the first metal layer, and the second metal layer; forming at least one second level disposed above the second metal layer; performing a first etch step including etching first holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching second holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where memory cells each include one memory transistor.

Described herein is a method of bonding and/or debonding substrates. In one embodiment, at least one of the surfaces of the substrates to be bonded is comprised of an oxide. In one embodiment, the surfaces of both substrates comprise an oxide. A wet etch may then be utilized to debond the substrates by etching away the layers that have been bonded. In one embodiment, a fusion bonding process is utilized to bond two substrates, at least one substrate having a silicon oxide surface. In one exemplary etch, a dilute hydrofluoric (DHF) etch is utilized to etch the bonded silicon oxide surface, allowing for two bonded substrates to be debonded. In another embodiment, the silicon oxide may be a low density silicon oxide. In one embodiment, both substrates may have a surface layer of the low density silicon oxide which may be fusion bonded together.

A semiconductor device, the device including: a plurality of transistors, where at least one of the plurality of transistors includes a first single crystal source, channel, and drain, where at least one of the plurality of transistors includes a second single crystal source, channel, and drain, where the second single crystal source, channel, and drain is disposed above the first single crystal source, channel, and drain, where at least one of the plurality of transistors includes a third single crystal source, channel, and drain, where the third single crystal source, channel, and drain is disposed above the second single crystal source, channel, and drain, where at least one of the plurality of transistors includes a fourth single crystal source, channel, and drain, and where the first single crystal source or drain, and the second single crystal source or drain each include n+ doped regions.

A method for controlling a process of manufacturing semiconductor devices, the method including: obtaining a first control grid associated with a first lithographic apparatus used for a first patterning process for patterning a first substrate; obtaining a second control grid associated with a second lithographic apparatus used for a second patterning process for patterning a second substrate; based on the first control grid and second control grid, determining a common control grid definition for a bonding step for bonding the first substrate and second substrate to obtain a bonded substrate; obtaining bonded substrate metrology data including data relating to metrology performed on the bonded substrate; and determining a correction for performance of the bonding step based on the bonded substrate metrology data, the determining a correction including determining a co-optimized correction for the bonding step and for the first patterning process and/or second patterning process.