A foundry-agnostic post-processing method for a wafer is provided. The wafer includes an active surface, a substrate and an intermediate layer interposed between the active surface and the substrate. The method includes removing the wafer from an output yield of a wafer processing foundry, thinning the substrate to the intermediate layer or within microns of the intermediate layer to expose a new surface and bonding the new surface to an alternate material substrate which provides for enhanced device performance as compared to the substrate.

A method for producing a semiconductor device involves forming a first transistor having a silicon substrate and a gate, and forming a second transistor, having a germanium substrate, on top of the first transistor. The second transistor is formed by forming a first gate of the second transistor on top of, and electrically coupled to, the gate of the first transistor, bonding the germanium substrate to the first gate of the second transistor so that the bonding does not damage the first transistor, and forming a second gate of the second transistor on the germanium substrate.

Embodiments of wafer bonding method and structures thereof are disclosed. The wafer bonding method can include performing a plasma activation treatment on a front surface of a first and a front surface of a second wafer; performing a silica sol treatment on the front surfaces of the first and the second wafers; performing a preliminary bonding process of the first and second wafer; and performing a heat treatment of the first and the second wafers to bond the front surface of the first wafer to the front surface of the second wafers.

A semiconductor structure with a high resistivity wafer includes a device wafer. The device wafer includes a front side and a back side. A semiconductor element is disposed on the front side. An interlayer dielectric covers the front side. A high resistivity wafer consists of an insulating material. A dielectric layer encapsulates the high resistivity wafer. The dielectric layer contacts the interlayer dielectric.

A method and a device for aligning two lenses, wherein the method is directed to aligning first and second optical partial systems of an optical system, which are arranged so as to be located opposite to one another. The method includes the steps of: projecting alignment marks into a first image plane of the first optical partial system, projecting the alignment marks from the first image plane onto a sensitive surface of the second optical partial system, and aligning the optical partial systems relative to one another, such that projections of the alignment marks in a depth of field of the sensitive surface are imaged at ideal positions.

A method for improving wafer bonding strength includes: Step S1: providing a silicon-based bonded wafer; Step S2: placing the bonded wafer in a microwave generating chamber; Step S3: raising the temperature in the microwave generating chamber and maintaining the temperature at a preset threshold by microwave heating; Step S4: after the bonded wafer reaches a predetermined temperature for a predetermined time period, shutting down the microwave power; and Step S5: cooling the bonded wafer. The present invention method can prevent waste of energy in the case of heating a small number of bonded wafers, and avoid a time-consuming preheating process. Therefore, the disclosed method is time-efficient and high-performance.

Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.

A method for bonding a first substrate to a second substrate on mutually facing contact surfaces of the substrates, wherein the first substrate is mounted on a first chuck and the second substrate is mounted on a second chuck, and wherein a plate is arranged between the second substrate and the second chuck, wherein the second substrate with the plate is deformed with respect to the second chuck before and/or during the bonding. Furthermore, the present invention relates to a corresponding device and a corresponding plate.

Die stacks and methods of making die stacks with very thin dies are disclosed. The die surfaces remain flat within a 5 micron tolerance despite the thinness of the die and the process steps of making the die stack. A residual flux height is kept below 50% of the spacing distance between adjacent surfaces or structures, e.g. in the inter-die spacing.

In example implementations of a heterogeneous substrate, the heterogeneous substrate includes a first material having an air trench, a second material coupled to the first material, a dielectric mask on a first portion of the second material and an active region that is grown on a remaining portion of the second material. An air gap may be formed in the air trench by the second material coupled to the first material. Defects in the second material may be contained to an area below the dielectric mask and the active region may remain defect free.