Disclosed herein is an apparatus for processing a substrate that forms a hole in a substrate while reducing a burr in the hole so that a module device can be inserted into the hole to reduce the thickness of a display device, and the display device using the apparatus. The apparatus for processing the substrate comprises a body configured to operably be rotatable, and a cylindrical cutting tip at an end of the body. The bottom surface of the cutting tip is in an acute angle with respect to a contact surface of the substrate to allow formation of a groove at the substrate.

Methods for fabricating semiconductor-metal-on-insulator (SMOI) structures include forming an acceptor wafer including an insulator material on a first semiconductor substrate, forming a donor wafer including a conductive material and an amorphous silicon material on a second semiconductor substrate, and bonding the amorphous silicon material of the donor wafer to the insulator material of the acceptor wafer. SMOI structures formed from such methods are also disclosed, as are semiconductor devices including such SMOI structures.

A process for attaching a first substrate to a second substrate by direct bonding, the first and second substrates comprising first and second surfaces, respectively, possessing an initial bonding energy. The process includes the successive steps of: providing the first and second substrates, attaching the first substrate to the second substrate by direct bonding with the first and second surfaces, at least partially debonding the first and second substrates so as to generate electrostatic charges on portions of the first and second surfaces, and rebonding the first substrate to the second substrate by direct bonding with said portions of the first and second surfaces.

A producing method includes a bonding process of bonding substrates in a pair one of which has thin film patterns and forming a bonded substrate, a cut forming process of forming a cut line CL1 on a border portion between the mounting area within the panel surface area and other area on the one substrate of the bonded substrate, a cutting process of cutting the bonded substrate into separated bonded substrate pieces, a grinding process of grinding the substrates in a pair that are outside the thin film pattern in each of the separated bonded substrates 50A along the outline and forming edge surfaces of the display panels each having the curved outline, and a removing process of cutting a part of the one substrate along the cut line and removing the part.

Micro pillars are formed in silicon. The micro pillars are used in boding the silicon to hetero-material such as III-V material, ceramics, or metals. In bonding the silicon to the hetero-material, indium is used as a bonding material and attached to the hetero-material. The bonding material is heated and the silicon and the hetero-material are pressed together. As the silicon and the hetero-material are pressed together, the micro pillars puncture the bonding material. In some embodiments, pedestals are used in the silicon as hard stops to align the hetero-material with the silicon.

Provided is a substrate bonding method for bonding a first substrate (11) and a second substrate (12) by sputter-etching, the substrate bonding method comprising: an activation step in which the surface of a first substrate (11) is irradiated with a beam (2) of ion particles of a gas (1) such as Ar and sputter-etched to thereby deposit sputtered particles (Ms) from the first substrate (11) on the surface of a second substrate (12), the first substrate (11) comprising at least one among a semiconductor material, a compound semiconductor material, and a metal material; and a bonding step in which the surface of the second substrate (12), on which the sputtered particles (Ms) from the first substrate (11) are deposited, and the surface of the substrate (11), which is sputter-etched, are overlapped and bonded with each other.

A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO.sub.2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

The disclosed technology relates generally to a method and system for micro assembling GaN materials and devices to form displays and lighting components that use arrays of small LEDs and high-power, high-voltage, and or high frequency transistors and diodes. GaN materials and devices can be formed from epitaxy on sapphire, silicon carbide, gallium nitride, aluminum nitride, or silicon substrates. The disclosed technology provides systems and methods for preparing GaN materials and devices at least partially formed on several of those native substrates for micro assembly.

A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic bonding structure embedded therein, wherein each metallic bonding structure contains a columnar grain microstructure. Furthermore, at least one columnar grain extends across a bonding interface that is present between the metallic bonding structures. The presence of the columnar grain microstructure in the metallic bonding structures, together with at least one columnar grain microstructure extending across the bonding interface between the two bonded metallic bonding structures, can provide a 3D bonded structure having mechanical bonding strength and electrical performance enhancements.

A multilayer composite bonding material for transient liquid phase bonding a semiconductor device to a metal substrate includes thermal stress compensation layers sandwiched between a pair of bonding layers. The thermal stress compensation layers may include a core layer with a first stiffness sandwiched between a pair of outer layers with a second stiffness that is different than the first stiffness such that a graded stiffness extends across a thickness of the thermal stress compensation layers. The thermal stress compensation layers have a melting point above a sintering temperature and the bonding layers have a melting point below the sintering temperature. The graded stiffness across the thickness of the thermal stress compensation layers compensates for thermal contraction mismatch between the semiconductor device and the metal substrate during cooling from the sintering temperature to ambient temperature.