Three-dimensional (3D) memory with control the array and control circuitry in separately processed and bonded wafers is described. In one example, a non-volatile storage component includes a first die including a three-dimensional (3D) array of non-volatile storage cells and a second die bonded with the first die. The second die includes CMOS (complementary metal oxide semiconductor) circuitry to access the 3D array of non-volatile storage cells. By processing the CMOS circuitry and array on separate wafers, the periphery CMOS and interconnects do not have to withstand the thermal cycles involved in processing the memory array, which enables optimizations for the CMOS transistors and the use low resistive material for interconnects.

A substrate bonding apparatus that brings a part of a surface of a first substrate and a part of a surface of a second substrate into contact to form contact regions at the parts, and then enlarges the contact regions to bond the first substrate and the second substrate includes: a temperature adjusting unit that adjusts a temperature of at least one of the first substrate and the second substrate such that positional misalignment between the first substrate and the second substrate does not exceed a threshold at least in a course of enlargement of the contact regions.

A method of manufacturing a semiconductor device includes disposing a peel-off layer on the second surface of the first substrate, wherein the second surface of the first substrate comprises semiconductor integrated circuits, and the peel-off layer does not extend to an outer peripheral portion of the first substrate, bonding a second substrate to the peel-off layer via a bonding layer, attaching a tape onto the first surface of the first substrate, wherein the tape comprises an adhesive agent having an adhesive strength capable of being lowered by UV irradiation, irradiating a portion of the adhesive agent provided at the outer peripheral portion with UV rays directed toward the first surface, and separating the first substrate from the second substrate at the adhesive agent portion and the peel-off layer portion.

A method is provided for preparing a semiconductor-on-insulator structure comprising a flowable insulating layer or a reflowable insulating layer.

It is formed, over a supporting body made of a ceramic, a bonding layer composed of one or more material selected from the group consisting of mullite, alumina, tantalum pentoxide, titanium oxide and niobium pentoxide. Neutralized beam is irradiated onto a surface of the bonding layer to activate the surface of the bonding layer. The surface of the bonding layer and the piezoelectric single crystal substrate are bonded by direct bonding.

A bonded body includes a supporting body composed of a ceramic, a bonding layer provided over a surface of the supporting body and composed of one or more material selected from the group consisting of mullite, alumina, tantalum pentoxide, titanium oxide and niobium pentoxide, and a piezoelectric single crystal substrate bonded with the bonding layer. The surface of the supporting body has an arithmetic average roughness Ra of 0.5 nm or larger and 5.0 nm or smaller.

A sheet jig of the present invention includes a center placement face on which a center region of a sheet is placed as having a plurality of first air holes to cause the center region of the sheet to be stuck, a peripheral upper face formed outside the center placement face at height being lower than the center placement face as having a plurality of second air holes to cause a peripheral region of the sheet to be stuck, and a slope face formed from the center placement face to the peripheral upper face.

To overcome the deficiencies of conventional rectangular circuit wafers, a glass substrate circuit wafer with an obtuse angle on the perimeter may be used. In one example, a glass substrate wafer may include a first circuit on a first portion of a glass substrate and a second circuit on a second portion of the glass substrate where the first portion has a first obtuse angle and the second portion has a second obtuse angle that is complementary to the first obtuse angle on the perimeter of the first portion to mate together to form an outer perimeter that comprises right angles.

A method for manufacturing an electronic device is disclosed, which includes the following steps: providing a first substrate and modifying a surface of the first substrate to obtain a modified surface; applying silane or derivatives thereof on the modified surface to form an adhesion precursor layer; heat-treating the adhesion precursor layer to form an adhesion layer; forming an inorganic layer on the adhesion layer; and forming an active unit on the inorganic layer, wherein the inorganic layer is disposed between the adhesion layer and the active unit.

A substrate bonding apparatus that brings a part of a surface of a first substrate and a part of a surface of a second substrate into contact in a state where a temperature difference is generated therebetween, to form contact regions at the parts, and then enlarges the contact regions to bond the first substrate and the second substrate, wherein enlargement of the contact regions starts before positional misalignment between the first substrate and the second substrate exceeds a threshold, and the threshold is set such that positional misalignment after the first substrate and the second substrate are bonded does not exceed a tolerated value.