A semiconductor device includes a first source/drain region on an upper surface of a semiconductor substrate that extends along a first direction to define a length and a second direction opposite the first direction to define a width. A channel region extends vertically in a direction perpendicular to the first and second directions from a first end contacting the first source/drain region to an opposing second end contacting a second source/drain region. A gate surrounds a channel portion of the channel region, and a first doped source/drain extension region is located between the first source/drain region and the channel portion. The first doped source/drain extension region has a thickness extending along the vertical direction. A second doped source/drain extension region is located between the second source/drain region and the channel portion. The second doped source/drain extension region has a thickness extending along the vertical direction that matches the first thickness.

A semiconductor device including a first source/drain region at a lower portion thereof, a second source/drain region at an upper portion thereof, a channel region between the first source/drain region and the second source/drain region and close to peripheral surfaces thereof, and a body region inside the channel region. The semiconductor device may further include a gate stack formed around a periphery of the channel region.

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer having a greater band gap than the first nitride semiconductor layer; a source electrode and a drain electrode on the second nitride semiconductor layer apart from each other; a third nitride semiconductor layer, between the source electrode and the drain electrode, containing a p-type first impurity and serving as a gate; and a fourth nitride semiconductor layer, between the third nitride semiconductor layer and the drain electrode, containing a p-type second impurity, wherein the average carrier concentration of the fourth nitride semiconductor layer is lower than the average carrier concentration of the third nitride semiconductor layer.

Disclosed are DRAM devices and methods of forming DRAM devices. One non-limiting method may include providing a device, the device including a plurality of angled structures formed from a substrate, a bitline and a dielectric between each of the plurality of angled structures, and a drain disposed along each of the plurality of angled structures. The method may further include providing a plurality of mask structures of a patterned masking layer over the plurality of angled structures, the plurality of mask structures being oriented perpendicular to the plurality of angled structures. The method may further include etching the device at a non-zero angle to form a plurality of pillar structures.

A method and apparatus for biasing regions of a substrate in a plasma-assisted processing chamber are provided. Biasing of the substrate, or regions thereof, increases the potential difference between the substrate and a plasma formed in the processing chamber thereby accelerating ions from the plasma towards the active surfaces of the substrate regions. A plurality of bias electrodes herein are spatially arranged across the substrate support in a pattern that is advantageous for managing uniformity of processing results across the substrate.

There is provided a method for producing, on one same wafer, at least one first transistor surmounted at least partially on a voltage stressed layer and a second transistor surmounted at least partially on a compression stressed layer, the method including providing a wafer including the first and the second transistors; forming at least one stressed nitride-based layer, on the first and the second transistors, the layer being voltage stressed; depositing a protective layer so as to cover a first zone of the layer, the first zone covering at least partially the first transistor and leaving a second zone of the layer uncovered, the second zone at least partially covering the second transistor; and modifying a type of stress of the second zone of the layer by implanting hydrogen-based ions from a plasma in the second zone, such that the second zone of the layer is compression stressed.

A semiconductor device includes a semiconductor substrate having a first dopant and a second dopant. A covalent atomic radius of a material of the semiconductor substrate is i) larger than a covalent atomic radius of the first dopant and smaller than a covalent atomic radius of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than the covalent atomic radius of the second dopant. The semiconductor device further includes a semiconductor layer on the semiconductor substrate and semiconductor device elements in the semiconductor layer. A vertical concentration profile of the first dopant decreases along at least 80% of a distance between an interface of the semiconductor substrate and the semiconductor layer to a surface of the semiconductor substrate opposite to the interface.

A method for forming a semiconductor device includes implanting first ions and second ions into a p-type silicon carbide layer from a first main side to form an implantation layer at the first main side. The implanting is performed by plasma immersion ion implantation in which the p-type silicon carbide layer is immersed in a plasma comprising the first ions and the second ions. The first ions can be ionized aluminum atoms and the second ions are different from the first ions.

A method of splitting a semiconductor wafer includes: forming one or more epitaxial layers on the semiconductor wafer; forming a plurality of device structures in the one or more epitaxial layers; forming a metallization layer and/or a passivation layer over the plurality of device structures; attaching a carrier to the semiconductor wafer with the one or more epitaxial layers, the carrier protecting the plurality of device structures and mechanically stabilizing the semiconductor wafer; forming a separation region within the semiconductor wafer, the separation region having at least one altered physical property which increases thermo-mechanical stress within the separation region relative to the remainder of the semiconductor wafer; and applying an external force to the semiconductor wafer such that at least one crack propagates along the separation region and the semiconductor wafer splits into two separate pieces, one of the pieces retaining the plurality of device structures.

A method and apparatus for biasing regions of a substrate in a plasma assisted processing chamber are provided. Biasing of the substrate, or regions thereof, increases the potential difference between the substrate and a plasma formed in the processing chamber thereby accelerating ions from the plasma towards the active surfaces of the substrate regions. A plurality of bias electrodes herein are spatially arranged across the substrate support in a pattern that is advantageous for managing uniformity of processing results across the substrate.