A method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include forming a first sacrificial layer including a first portion and a second portion having a thickness thicker than a thickness of the first portion, forming a stack including first material layers and second material layers alternating with each other on the first sacrificial layer, forming a channel structure passing through the stack and extending to the first portion, forming a slit passing through the stack and extending to the second portion, removing the first sacrificial layer through the slit to form a first opening, and forming a second source layer connected to the channel structure in the first opening.

A method for manufacturing a semiconductor device includes forming a first semiconductor layer having a first concentration of germanium on a semiconductor substrate, a second semiconductor layer having a second concentration of germanium on the first semiconductor layer, and a third semiconductor layer having a third concentration of germanium on the second semiconductor layer. The method also includes patterning the first, second and third semiconductor layers into at least one fin, and reducing a width of the second semiconductor layer of the at least one fin. In the method, a bottom source/drain region is grown from the substrate adjacent a base portion of the at least one fin, a gate structure is formed on and around the second semiconductor layer, and a top source/drain region is grown from the third semiconductor layer.

When an insulated gate bipolar transistor is incorporated in a drive circuit of a flash lamp, so that a light emission pattern of the flash lamp is freely defined, a temperature change pattern of a surface of a semiconductor wafer that receives the emission of flash light can be adjusted. The length of diffusion of impurities can be controlled by rising a surface temperature of the semiconductor wafer from a preheating temperature to a diffusion temperature through emission of flash light and maintaining the surface temperature at the diffusion temperature for a time period not shorter than 1 millisecond and not longer than 10 milliseconds. Subsequently, the impurities can be activated by rising the surface temperature of the semiconductor wafer from the diffusion temperature to an activation temperature.

A method of making a semiconductor device including forming a first blanket layer on a substrate; forming a second blanket layer on the first blanket layer; patterning a first fin of a first transistor region and a second fin of a second transistor region in the first blanket layer and the second blanket layer; depositing a mask on the second transistor region; removing the first fin to form a trench; growing a first semiconductor layer in the trench where the first fin was removed; and growing a second semiconductor layer on the first semiconductor layer.

A method for manufacturing a semiconductor device includes forming a first semiconductor layer having a first concentration of germanium on a semiconductor substrate, a second semiconductor layer having a second concentration of germanium on the first semiconductor layer, and a third semiconductor layer having a third concentration of germanium on the second semiconductor layer. The method also includes patterning the first, second and third semiconductor layers into at least one fin, and reducing a width of the second semiconductor layer of the at least one fin. In the method, a bottom source/drain region is grown from the substrate adjacent a base portion of the at least one fin, a gate structure is formed on and around the second semiconductor layer, and a top source/drain region is grown from the third semiconductor layer.

Fin field-effect transistors are provided. A fin field-effect transistor includes a semiconductor substrate; a plurality of fins on the semiconductor substrate; a gate structure across the fins by covering portions of top and side surfaces of the fins, providing portions of the fins under the gate structure as channel regions; lightly doped regions in the fins at both sides of the gate structure; doped source/drain regions in the fins at both sides of the gate structure; and counter doped regions in fins and between the lightly doped regions and the doped source/drain regions.

A semiconductor device includes trench gate structures that extend from a first surface into a silicon carbide portion. A shielding region between a drift zone and the trench gate structures along a vertical direction orthogonal to the first surface forms an auxiliary pn junction with the drift zone. Channel regions and the trench gate structures are successively arranged along a first horizontal direction. The channel regions are arranged between a source region and a current spread region along a second horizontal direction orthogonal to the first horizontal direction. Portions of mesa sections between neighboring trench gate structures fully deplete at a gate voltage within an absolute maximum rating of the semiconductor device.

A LTPS TFT comprises a substrate, and a buffer layer, a low temperature polysilicon layer, a source contact area, a drain contact area, a gate insulating layer, a gate layer, a dielectric layer, a source and a drain disposed on the substrate successively. The source contact area and the drain contact area are doped with metal ions individually. The source and the drain are connecting with the source and drain contact areas separately through the dielectric layer. The metal ions include at least one of Cu.sup.2+, Al.sup.3+, Mg.sup.2+, Zn.sup.2+ and Ni.sup.2+. A method of fabricating the LTPS TFT is also provided. An annealing is performed for driving individually metal ions of the insulation metal oxide layer into the source contact area and the drain contact area. Thus, the step of implanting p-type ions can be omitted, the procedure can be significantly simplified, and the manufacturing cost can be reduced.

A fin field-effect transistor (fin-FET) includes a substrate having a plurality of discrete fin structures thereon; a chemical oxide layer on at least a sidewall of a fin structure; a doped layer containing doping ions on the chemical oxide layer; and a doped region in the fin structure containing doping ions diffused from the doping ions in the doped layer.

Disclosed is a semiconductor structure including a lateral heterojunction bipolar transistor (HBT). The structure includes a substrate (e.g., a silicon substrate), an insulator layer on the substrate, and a semiconductor layer (e.g., a silicon germanium layer) on the insulator layer. The structure includes a lateral HBT with three terminals including a collector, an emitter, and a base, which is positioned laterally between the collector and the emitter and which can include a silicon germanium intrinsic base region for improved performance. Additionally, the collector and/or the emitter includes: a first region, which is epitaxially grown within a trench that extends through the semiconductor layer and the insulator layer to the substrate; and a second region, which is epitaxially grown on the first region. The connection(s) of the collector and/or the emitter to the substrate effectively form thermal exit path(s) and minimize self-heating. Also disclosed is a method for forming the structure.