Fin field-effect transistors are provided. A fin field-effect transistor includes a semiconductor substrate; a plurality of fins on the semiconductor substrate; a gate structure across the fins by covering portions of top and side surfaces of the fins, providing portions of the fins under the gate structure as channel regions; lightly doped regions in the fins at both sides of the gate structure; doped source/drain regions in the fins at both sides of the gate structure; and counter doped regions in fins and between the lightly doped regions and the doped source/drain regions.

A method of fabrication of a semiconductor device including implementation of fabrication of at least one stack made on a substrate, including at least one first portion of a first semiconductor and at least one second portion of a second semiconductor which is different from the first semiconductor, so the thickness of at least the first portion is substantially equal to the thickness of at least one nanostructure, and wherein the first or second semiconductor is capable of being selectively etched relative to the second or first semiconductor, respectively, fabrication, on a part of the stack, of external spacers and at least one dummy gate, etching of the stack such that the remaining parts of the first and second portions are arranged beneath the dummy gate and beneath the external spacers and form a stack of nanowires, after the etching of the stack, thermal treatment of the stack of nanowires.

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A stack of alternating nanosheets of sacrificial semiconductor material nanosheets and semiconductor material nanosheets located on a surface of a substrate are provided, wherein a sacrificial gate structure and a dielectric spacer material layer straddle over the nanosheet stack. End portions of each of the sacrificial semiconductor material nanosheets are recessed. A dielectric spacer is formed within each recess. Doped semiconductor portions are formed on the physically exposed sidewalls of each semiconductor material nanosheet and on the surface of the substrate. The semiconductor structure is thermally annealed. The sacrificial gate, each sacrificial semiconductor material nanosheet, and the dielectric spacer are each removed. A doped epitaxial material structure is formed in regions occupied by each sacrificial semiconductor material nanosheet, where the doped epitaxial material structure wraps around each suspended semiconductor material nanosheet.

A semiconductor device that includes at least one fin structure and a gate structure present on a channel portion of the fin structure. An epitaxial semiconductor material is present on at least one of a source region portion and a drain region portion on the fin structure. The epitaxial semiconductor material includes a first portion having a substantially conformal thickness on a lower portion of the fin structure sidewall and a second portion having a substantially diamond shape that is present on an upper surface of the source portion and drain portion of the fin structure. A spacer present on first portion of the epitaxial semiconductor material.

A semiconductor device includes a substrate; a fin protruding above the substrate, the fin including a compound semiconductor material that includes a semiconductor material and a first dopant, the first dopant having a different lattice constant than the semiconductor material, where a concentration of the first dopant in the fin changes along a first direction from an upper surface of the fin toward the substrate; a gate structure over the fin; a channel region in the fin and directly under the gate structure; and source/drain regions on opposing sides of the gate structure, the source/drain regions including a second dopant, where a concentration of the second dopant at a first location within the channel region is higher than that at a second location within the channel region, where the concentration of the first dopant at the first location is lower than that at the second location.

Some embodiments include a method of forming an integrated assembly. A first stack is formed over a conductive structure. The first stack includes a second layer between first and third layers. The first and third layers are conductive. A first opening is formed through the first stack. A sacrificial material is formed within the first opening. A second stack is formed over the first stack. The second stack has alternating first and second levels. A second opening is formed through the second stack and through the sacrificial material. First semiconductor material is formed within the second opening. A third opening is formed through the second stack, through the third layer, and to the second layer. The second layer is removed, forming a conduit. Second semiconductor material is formed within the conduit. Dopant is out-diffused from the second semiconductor material into the first semiconductor material. Some embodiments include integrated assemblies.

A method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include forming a first sacrificial layer including a first portion and a second portion having a thickness thicker than a thickness of the first portion, forming a stack including first material layers and second material layers alternating with each other on the first sacrificial layer, forming a channel structure passing through the stack and extending to the first portion, forming a slit passing through the stack and extending to the second portion, removing the first sacrificial layer through the slit to form a first opening, and forming a second source layer connected to the channel structure in the first opening.

A fin field-effect transistor (fin-FET) includes a substrate having a plurality of discrete fin structures thereon; a chemical oxide layer on at least a sidewall of a fin structure; a doped layer containing doping ions on the chemical oxide layer; and a doped region in the fin structure containing doping ions diffused from the doping ions in the doped layer.

Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.

Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.